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| "cell_footprint": "sky130_fd_sc_hdll__sdlclkp", |
| "cell_leakage_power": 0.0, |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
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| "pg_pin,VPB": { |
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| "voltage_name": "VPWR" |
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| "clock_gate_clock_pin": "true", |
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| "timing_sense": "positive_unate", |
| "timing_type": "combinational_fall", |
| "when": "(!GATE&!SCE)" |
| } |
| ] |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,SCE": { |
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| "clock": "false", |
| "clock_gate_test_pin": "true", |
| "direction": "input", |
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| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001821, |
| "timing": [ |
| { |
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| 0.01, |
| 0.5, |
| 1.5 |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_3_3_1": { |
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| 0.01, |
| 0.5, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
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| [ |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10.0 |
| }, |
| { |
| "fall_constraint,vio_3_3_1": { |
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| 0.01, |
| 0.5, |
| 1.5 |
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| "index_2": [ |
| 0.01, |
| 0.5, |
| 1.5 |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.01, |
| 0.5, |
| 1.5 |
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| "index_2": [ |
| 0.01, |
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| [ |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10.0 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
