{
  "area": 31.28,
  "cell_footprint": "sky130_fd_sc_hdll__dfrtp",
  "cell_leakage_power": 0.0,
  "ff,IQ,IQ_N": {
    "clear": "!RESET_B",
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
  },
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    "capacitance": 0.001471,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.001298,
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          0.0793701,
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      "rise_power,power_inputs_1": {
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    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001495,
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      "related_pin": "CLK",
      "rise_constraint,constraint_3_0_1": {
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      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
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    "clock": "false",
    "direction": "input",
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    "max_transition": 5.0,
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    "related_power_pin": "VPWR",
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        "related_pin": "CLK",
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          "index_2": [
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10.0
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      {
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        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            5.0
          ],
          "index_2": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10.0
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    ]
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    "direction": "output",
    "function": "IQ",
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        "fall_power,scalar": {
          "values": [
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          ]
        },
        "related_pin": "CLK",
        "rise_power,power_outputs_1": {
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        "when": "(D&RESET_B)"
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      {
        "fall_power,power_outputs_1": {
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        "related_pin": "CLK",
        "rise_power,scalar": {
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        "when": "(!D&RESET_B)"
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      {
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        "when": "(!CLK&D)"
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      {
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        "related_pin": "RESET_B",
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        "when": "(CLK&!D)"
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      {
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        "when": "(CLK&D)"
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    ],
    "max_capacitance": 0.438319,
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    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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        "related_pin": "CLK",
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      "rise_power,power_inputs_1": {
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    "max_transition": 5.0,
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        "sim_opt": "runlvl=5 accurate=1",
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      {
        "related_pin": "CLK",
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            [
              2.6565655,
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "removal_rising",
        "violation_delay_degrade_pct": 10.0
      },
      {
        "fall_constraint,constraint_3_0_1": {
          "index_1": [
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            2.5,
            5.0
          ],
          "values": [
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            3.6163395,
            6.2519998
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        },
        "related_pin": "RESET_B",
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "min_pulse_width",
        "violation_delay_degrade_pct": 10.0
      }
    ]
  }
}