| { | |
| "area": 40.0384, | |
| "cell_footprint": "sky130_fd_sc_hdll__sdfsbp", | |
| "cell_leakage_power": 0.0, | |
| "ff,IQ,IQ_N": { | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)", | |
| "preset": "!SET_B" | |
| }, | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,CLK": { | |
| "capacitance": 0.00194, | |
| "clock": "true", | |
| "direction": "input", | |
| "fall_capacitance": 0.001753, | |
| "internal_power": { | |
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| 0.01, | |
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| 0.0531329, | |
| 0.122474, | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.001966, | |
| "timing": { | |
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| 0.01, | |
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| 1.5 | |
| ], | |
| "values": [ | |
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| }, | |
| "related_pin": "CLK", | |
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| 0.01, | |
| 0.5, | |
| 1.5 | |
| ], | |
| "values": [ | |
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| }, | |
| "sim_opt": "runlvl=5 accurate=1", | |
| "timing_type": "min_pulse_width", | |
| "violation_delay_degrade_pct": 10.0 | |
| } | |
| }, | |
| "pin,D": { | |
| "capacitance": 0.001829, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001718, | |
| "internal_power": { | |
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| "nextstate_type": "data", | |
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| }, | |
| "related_pin": "CLK", | |
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| [ | |
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| }, | |
| "sim_opt": "runlvl=5 accurate=1", | |
| "timing_type": "setup_rising", | |
| "violation_delay_degrade_pct": 10.0 | |
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| { | |
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| }, | |
| "related_pin": "CLK", | |
| "rise_constraint,vio_3_3_1": { | |
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| "sim_opt": "runlvl=5 accurate=1", | |
| "timing_type": "hold_rising", | |
| "violation_delay_degrade_pct": 10.0 | |
| } | |
| ] | |
| }, | |
| "pin,Q": { | |
| "direction": "output", | |
| "function": "IQ", | |
| "internal_power": [ | |
| { | |
| "fall_power,scalar": { | |
| "values": [ | |
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| ] | |
| }, | |
| "related_pin": "CLK", | |
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| { | |
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| "related_power_pin": "VPWR", | |
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| "related_pin": "CLK", | |
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| "timing_sense": "positive_unate", | |
| "timing_type": "rising_edge", | |
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| { | |
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