{
 "description": "2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR.",
 "equation": "X = ((!A1 & !A2) | (B1 & B2))",
 "file_prefix": "sky130_fd_sc_hdll__a2bb2o",
 "library": "sky130_fd_sc_hdll",
 "name": "a2bb2o",
 "parameters": [],
 "ports": [
  [
   "signal",
   "X",
   "output",
   ""
  ],
  [
   "signal",
   "A1_N",
   "input",
   ""
  ],
  [
   "signal",
   "A2_N",
   "input",
   ""
  ],
  [
   "signal",
   "B1",
   "input",
   ""
  ],
  [
   "signal",
   "B2",
   "input",
   ""
  ],
  [
   "power",
   "VPWR",
   "input",
   "supply1"
  ],
  [
   "power",
   "VGND",
   "input",
   "supply0"
  ],
  [
   "power",
   "VPB",
   "input",
   "supply1"
  ],
  [
   "power",
   "VNB",
   "input",
   "supply0"
  ]
 ],
 "type": "cell",
 "verilog_name": "sky130_fd_sc_hdll__a2bb2o"
}