Fixing the `power_gating_pin`.

Updating sky130_fd_sc_hdll 0.1.0.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v65.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v65.lib.json
index d19d2b1..f125a1c 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v65.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v95.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v95.lib.json
index f0824e6..0c8cfee 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v95.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v56.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v56.lib.json
index d3387c4..f74aa59 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v56.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v65.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v65.lib.json
index cae8ae1..0378f94 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v65.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v95.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v95.lib.json
index 8bcfc21..d3391e1 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v95.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_100C_1v60.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_100C_1v60.lib.json
index f7b88c1..551263c 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_100C_1v60.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v28.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v28.lib.json
index 245670e..4b4d437 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v28.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v44.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v44.lib.json
index ce4cb6e..38a1472 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v44.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v60.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v60.lib.json
index f19435e..d72a1a1 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v60.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v76.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v76.lib.json
index 844223e..681b8d3 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v76.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_1__tt_025C_1v80.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_1__tt_025C_1v80.lib.json
index 5595370..6d5c6c8 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_1__tt_025C_1v80.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_1__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v65.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v65.lib.json
index 21e2661..68b2ae0 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v65.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v95.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v95.lib.json
index 51205a7..db2262d 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v95.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v56.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v56.lib.json
index e73de1f..9bfd265 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v56.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v65.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v65.lib.json
index 0aea76e..5d1dbbb 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v65.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v95.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v95.lib.json
index 40ae48d..5a5de38 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v95.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_100C_1v60.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_100C_1v60.lib.json
index 617f618..83321aa 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_100C_1v60.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v28.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v28.lib.json
index bae2335..485ca60 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v28.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v44.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v44.lib.json
index 7285cea..794558b 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v44.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v60.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v60.lib.json
index ba3b7d0..92ef9b6 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v60.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v76.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v76.lib.json
index b9ddcaf..ea9cf5e 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v76.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_2__tt_025C_1v80.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_2__tt_025C_1v80.lib.json
index d85a225..76bfe8f 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_2__tt_025C_1v80.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_2__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v65.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v65.lib.json
index 6feb53f..e7549b5 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v65.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v95.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v95.lib.json
index fcfee0d..ad0f656 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v95.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v56.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v56.lib.json
index 74553ea..58f0ca9 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v56.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v65.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v65.lib.json
index a68878a..52feb0b 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v65.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v95.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v95.lib.json
index 44e08f6..866221d 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v95.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_100C_1v60.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_100C_1v60.lib.json
index 42cd028..c8af270 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_100C_1v60.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v28.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v28.lib.json
index 2c82268..db3aa7c 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v28.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v44.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v44.lib.json
index 82068d5..c9971a4 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v44.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v60.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v60.lib.json
index 75f5156..559b115 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v60.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v76.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v76.lib.json
index fc7fae2..fd01992 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v76.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211o/sky130_fd_sc_hdll__a211o_4__tt_025C_1v80.lib.json b/cells/a211o/sky130_fd_sc_hdll__a211o_4__tt_025C_1v80.lib.json
index 65192a1..6fe1706 100644
--- a/cells/a211o/sky130_fd_sc_hdll__a211o_4__tt_025C_1v80.lib.json
+++ b/cells/a211o/sky130_fd_sc_hdll__a211o_4__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v65.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v65.lib.json
index 0e05f03..f2bb580 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v65.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v95.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v95.lib.json
index c8a65bd..b2b0aa3 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v95.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v56.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v56.lib.json
index 1611696..bb56b92 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v56.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v65.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v65.lib.json
index 1eb64f7..6d64703 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v65.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v95.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v95.lib.json
index 3698608..6ed0d4e 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v95.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_100C_1v60.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_100C_1v60.lib.json
index aae2e35..f36d8da 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_100C_1v60.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v28.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v28.lib.json
index cd27569..ee682d1 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v28.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v44.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v44.lib.json
index 0d2c9ae..04eded1 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v44.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v60.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v60.lib.json
index da6d477..7902c6c 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v60.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v76.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v76.lib.json
index 9b736b1..a83be04 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v76.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__tt_025C_1v80.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__tt_025C_1v80.lib.json
index e2f4876..6c72c6a 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__tt_025C_1v80.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_1__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v65.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v65.lib.json
index 85ac043..a912c4e 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v65.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v95.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v95.lib.json
index a30bca4..4d2fdf6 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v95.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v56.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v56.lib.json
index 011d9e7..0e5a173 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v56.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v65.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v65.lib.json
index 7496608..9df1c77 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v65.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v95.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v95.lib.json
index 53ca53e..8ed988c 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v95.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_100C_1v60.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_100C_1v60.lib.json
index 5d66f0d..ece9edb 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_100C_1v60.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v28.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v28.lib.json
index 9cf793f..6d812c9 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v28.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v44.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v44.lib.json
index a7dfda9..d0e2d3d 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v44.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v60.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v60.lib.json
index 7a460c1..fd9034b 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v60.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v76.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v76.lib.json
index 296c58d..69083a5 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v76.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__tt_025C_1v80.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__tt_025C_1v80.lib.json
index b647dec..1b2360f 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__tt_025C_1v80.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_2__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v65.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v65.lib.json
index f29b112..44d818a 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v65.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v95.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v95.lib.json
index 4651d25..8df5cf7 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v95.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v56.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v56.lib.json
index b4dffed..4b1ea19 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v56.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v65.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v65.lib.json
index 5793d4e..3b29e1f 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v65.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v95.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v95.lib.json
index c90f646..36c4f25 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v95.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_100C_1v60.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_100C_1v60.lib.json
index 3f745f8..42ca733 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_100C_1v60.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v28.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v28.lib.json
index 5596e48..5621861 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v28.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v44.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v44.lib.json
index 238a8ac..9ac9d24 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v44.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v60.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v60.lib.json
index ec3874c..e519177 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v60.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v76.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v76.lib.json
index 3b1f72b..f44f4ae 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v76.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__tt_025C_1v80.lib.json b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__tt_025C_1v80.lib.json
index cebf52a..ce123e9 100644
--- a/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__tt_025C_1v80.lib.json
+++ b/cells/a211oi/sky130_fd_sc_hdll__a211oi_4__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v65.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v65.lib.json
index 2319c40..c685ed0 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v65.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v95.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v95.lib.json
index 83e2ec7..000522c 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v95.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v56.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v56.lib.json
index eac02b3..4a8565d 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v56.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v65.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v65.lib.json
index 6966d15..8834663 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v65.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v95.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v95.lib.json
index ba2ea81..562acf2 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v95.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_100C_1v60.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_100C_1v60.lib.json
index d21f87a..c85f449 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_100C_1v60.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v28.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v28.lib.json
index 659f257..3890dcf 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v28.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v44.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v44.lib.json
index ba8e739..2d71921 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v44.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v60.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v60.lib.json
index 630b5e5..f6022fb 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v60.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v76.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v76.lib.json
index b0bc85f..9b2af8c 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v76.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__tt_025C_1v80.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__tt_025C_1v80.lib.json
index 4724df2..966d4ad 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__tt_025C_1v80.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_1__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v65.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v65.lib.json
index 1bbd251..d820ad4 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v65.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v95.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v95.lib.json
index 26ad9a8..34abc87 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v95.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v56.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v56.lib.json
index c3d26f5..7439f90 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v56.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v65.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v65.lib.json
index 11f655a..dabf9aa 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v65.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v95.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v95.lib.json
index 565d56d..a471394 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v95.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_100C_1v60.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_100C_1v60.lib.json
index 66c26d4..89606a6 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_100C_1v60.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v28.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v28.lib.json
index da53ed8..12c21de 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v28.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v44.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v44.lib.json
index 051138f..3960615 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v44.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v60.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v60.lib.json
index 25a2a18..1de04ff 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v60.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v76.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v76.lib.json
index 18b27bc..2197760 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v76.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__tt_025C_1v80.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__tt_025C_1v80.lib.json
index 039b6d5..e138484 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__tt_025C_1v80.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_2__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v65.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v65.lib.json
index 06541a8..08b6b1c 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v65.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v95.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v95.lib.json
index f262052..2331cff 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v95.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v56.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v56.lib.json
index 109c108..385f6d6 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v56.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v65.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v65.lib.json
index a057658..4e42826 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v65.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v95.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v95.lib.json
index c48a90a..c12cb0f 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v95.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_100C_1v60.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_100C_1v60.lib.json
index 1eac637..94323fe 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_100C_1v60.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v28.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v28.lib.json
index 2080244..b2d8a59 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v28.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v44.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v44.lib.json
index 731b2a7..879a082 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v44.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v60.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v60.lib.json
index 91e13ae..72248ea 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v60.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v76.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v76.lib.json
index 4e13a65..20f497b 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v76.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__tt_025C_1v80.lib.json b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__tt_025C_1v80.lib.json
index 52b6904..eec40bb 100644
--- a/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__tt_025C_1v80.lib.json
+++ b/cells/a21bo/sky130_fd_sc_hdll__a21bo_4__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v65.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v65.lib.json
index 0d60ad8..6efdaea 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v65.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v95.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v95.lib.json
index 02bb696..b080035 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v95.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v56.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v56.lib.json
index c8fc6a1..a6121b8 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v56.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v65.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v65.lib.json
index 2de8cbd..1d3c25d 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v65.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v95.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v95.lib.json
index ff5b0ae..4a6923e 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v95.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_100C_1v60.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_100C_1v60.lib.json
index 0a98622..237ae5c 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_100C_1v60.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v28.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v28.lib.json
index 9539aee..22d5f7c 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v28.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v44.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v44.lib.json
index a4e46c3..5ea24f9 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v44.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v60.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v60.lib.json
index 1f147ca..a7c050b 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v60.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v76.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v76.lib.json
index 6d1eaea..521706e 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v76.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__tt_025C_1v80.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__tt_025C_1v80.lib.json
index 785184d..1ab4343 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__tt_025C_1v80.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_1__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v65.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v65.lib.json
index 023e58a..8fc914d 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v65.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v95.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v95.lib.json
index bb69f93..73f6c3a 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v95.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v56.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v56.lib.json
index db12ab9..dcbf9f0 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v56.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v65.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v65.lib.json
index ccfd346..7547d93 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v65.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v95.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v95.lib.json
index 05f4217..a6dc4c0 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v95.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_100C_1v60.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_100C_1v60.lib.json
index 33d47c9..6bf2709 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_100C_1v60.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v28.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v28.lib.json
index 155340d..271bab0 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v28.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v44.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v44.lib.json
index 95e0f4e..9d05687 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v44.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v60.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v60.lib.json
index d9231e7..07a537a 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v60.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v76.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v76.lib.json
index 8610abd..49c7c42 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v76.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__tt_025C_1v80.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__tt_025C_1v80.lib.json
index 86299ef..a2469f0 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__tt_025C_1v80.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_2__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v65.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v65.lib.json
index db82e8f..1897b93 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v65.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v95.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v95.lib.json
index f1d93d0..710c808 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v95.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v56.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v56.lib.json
index 86815a9..dd9d4fa 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v56.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v65.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v65.lib.json
index 24caa42..6c93dd1 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v65.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v95.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v95.lib.json
index bbe3e3b..19a8af3 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v95.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_100C_1v60.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_100C_1v60.lib.json
index 62b37fe..05c6c85 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_100C_1v60.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v28.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v28.lib.json
index 03b5805..3b3fcb9 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v28.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v44.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v44.lib.json
index 5e23edc..4f4d5ec 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v44.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v60.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v60.lib.json
index 050b9b7..5f7b77c 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v60.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v76.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v76.lib.json
index 13c9ced..b489d2f 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v76.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__tt_025C_1v80.lib.json b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__tt_025C_1v80.lib.json
index c9b4acc..d5c7675 100644
--- a/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__tt_025C_1v80.lib.json
+++ b/cells/a21boi/sky130_fd_sc_hdll__a21boi_4__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v65.lib.json
index d34fa08..30665ce 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v95.lib.json
index 718b11d..ab410cc 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v56.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v56.lib.json
index 505bf7b..0f4191e 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v56.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v65.lib.json
index 9cd8e3f..d6d7791 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v95.lib.json
index 57155ea..60cef09 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_100C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_100C_1v60.lib.json
index 3ff4943..b1c4c1e 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_100C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v28.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v28.lib.json
index 7d43509..c7dccc3 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v28.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v44.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v44.lib.json
index 740adb9..6309ada 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v44.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v60.lib.json
index c1f4de8..7c365a3 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v76.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v76.lib.json
index ec542c1..05d98ad 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v76.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_1__tt_025C_1v80.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_1__tt_025C_1v80.lib.json
index a1c44b4..591e181 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_1__tt_025C_1v80.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_1__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v65.lib.json
index d8a6d4f..5f03847 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v95.lib.json
index 23aa644..4fa2159 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v56.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v56.lib.json
index 51d85a1..b029e34 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v56.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v65.lib.json
index 6cc7770..aedfc83 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v95.lib.json
index 10d3f97..6e949a1 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_100C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_100C_1v60.lib.json
index e86a95b..5552e9f 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_100C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v28.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v28.lib.json
index 306c917..4ac8869 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v28.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v44.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v44.lib.json
index dc8f6df..bd4147e 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v44.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v60.lib.json
index b3076e5..5f1d97a 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v76.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v76.lib.json
index b5115c1..a6aa476 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v76.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_2__tt_025C_1v80.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_2__tt_025C_1v80.lib.json
index e88f2d1..d669ffb 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_2__tt_025C_1v80.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_2__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v65.lib.json
index b08c48a..c42198a 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v95.lib.json
index 850d119..a79e2cf 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v56.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v56.lib.json
index 2944b0c..7885f73 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v56.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v65.lib.json
index 196973c..91b754a 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v95.lib.json
index e3bfc2f..c40d833 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_100C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_100C_1v60.lib.json
index a427697..88981f1 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_100C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v28.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v28.lib.json
index 4acd665..e60b52d 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v28.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v44.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v44.lib.json
index e9c28aa..20aa6a9 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v44.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v60.lib.json
index 2857ec3..2499374 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v76.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v76.lib.json
index b909351..3972f17 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v76.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_4__tt_025C_1v80.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_4__tt_025C_1v80.lib.json
index dc020ed..f970f0e 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_4__tt_025C_1v80.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_4__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v65.lib.json
index 1f4eed7..83c0d1a 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v95.lib.json
index 36f9eae..6535ce7 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v56.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v56.lib.json
index e949bae..a966221 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v56.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v56.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v65.lib.json
index 61ff0d5..b9fd173 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v95.lib.json
index 05d732e..9ff848e 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_100C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_100C_1v60.lib.json
index e22c77f..a36eeab 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_100C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v28.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v28.lib.json
index 1095fc5..4ee3859 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v28.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v28.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v44.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v44.lib.json
index 0951302..46ebdc8 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v44.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v44.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v60.lib.json
index 887e46b..6bca414 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v76.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v76.lib.json
index c0189a6..fec6656 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v76.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__ss_n40C_1v76.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_6__tt_025C_1v80.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_6__tt_025C_1v80.lib.json
index a215255..7fad932 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_6__tt_025C_1v80.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_6__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v65.lib.json
index 327c691..5752c63 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v95.lib.json
index 195115f..2b7ebc4 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v56.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v56.lib.json
index 7c8f945..f602ebe 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v56.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v56.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v65.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v65.lib.json
index 108ee86..f8dcba5 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v65.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v95.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v95.lib.json
index a80682d..a5ddcc9 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v95.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_100C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_100C_1v60.lib.json
index 08f2bcb..3dd1be0 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_100C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v28.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v28.lib.json
index 28f2150..485d2e1 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v28.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v28.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v44.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v44.lib.json
index d4e3b6e..1af5db4 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v44.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v44.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v60.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v60.lib.json
index a0e6e55..24c641a 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v60.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v76.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v76.lib.json
index 6aa44a7..b557cf0 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v76.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__ss_n40C_1v76.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21o/sky130_fd_sc_hdll__a21o_8__tt_025C_1v80.lib.json b/cells/a21o/sky130_fd_sc_hdll__a21o_8__tt_025C_1v80.lib.json
index f84ff7e..4056d58 100644
--- a/cells/a21o/sky130_fd_sc_hdll__a21o_8__tt_025C_1v80.lib.json
+++ b/cells/a21o/sky130_fd_sc_hdll__a21o_8__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v65.lib.json
index 1427852..a1b394a 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v95.lib.json
index 1a5feab..56828d5 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v56.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v56.lib.json
index 60a6dfa..619a016 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v56.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v65.lib.json
index 4c5a142..5bf15d3 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v95.lib.json
index 140db85..aa9a747 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_100C_1v60.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_100C_1v60.lib.json
index 3dd1b41..efc7571 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_100C_1v60.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v28.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v28.lib.json
index 243309a..7932ef0 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v28.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v44.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v44.lib.json
index a5f271f..98c469a 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v44.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v60.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v60.lib.json
index 64c4953..39dd306 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v60.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v76.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v76.lib.json
index 49ec9f5..f19b0df 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v76.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__tt_025C_1v80.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__tt_025C_1v80.lib.json
index f9b00db..39f76e7 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__tt_025C_1v80.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_1__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v65.lib.json
index 877bf45..047b858 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v95.lib.json
index 8085437..c9b5db5 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v56.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v56.lib.json
index 1f6d907..3848aca 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v56.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v65.lib.json
index f450760..37387f9 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v95.lib.json
index 06b3609..e9c1803 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_100C_1v60.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_100C_1v60.lib.json
index 9cb89b4..679699e 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_100C_1v60.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v28.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v28.lib.json
index 1c9b3f9..8129895 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v28.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v44.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v44.lib.json
index 0066928..8f9e245 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v44.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v60.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v60.lib.json
index 03bbddf..6eef701 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v60.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v76.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v76.lib.json
index 4c39e5b..4672021 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v76.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__tt_025C_1v80.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__tt_025C_1v80.lib.json
index 42c6eb8..0ae755b 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__tt_025C_1v80.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_2__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v65.lib.json
index 1ff751b..7ea7a83 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v95.lib.json
index 11b7609..d116872 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_100C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v56.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v56.lib.json
index c37bd9e..3feb7d0 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v56.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v65.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v65.lib.json
index 7e9559c..a3fb030 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v65.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v65.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v95.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v95.lib.json
index 540548f..fea58a4 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v95.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ff_n40C_1v95.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_100C_1v60.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_100C_1v60.lib.json
index facda09..a731a55 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_100C_1v60.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_100C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v28.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v28.lib.json
index 7871673..c4404f5 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v28.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v44.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v44.lib.json
index 68ca948..1103eb6 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v44.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v60.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v60.lib.json
index 7694733..957fa42 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v60.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v60.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v76.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v76.lib.json
index b5d6e21..a403d9e 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v76.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__tt_025C_1v80.lib.json b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__tt_025C_1v80.lib.json
index d43618d..0cb3016 100644
--- a/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__tt_025C_1v80.lib.json
+++ b/cells/a21oi/sky130_fd_sc_hdll__a21oi_4__tt_025C_1v80.lib.json
@@ -38,20 +38,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v65.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v65.lib.json
index b29d4b1..5200f00 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v65.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v65.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v95.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v95.lib.json
index a7030c2..f1a8551 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v95.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_100C_1v95.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v56.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v56.lib.json
index 048d988..5c702dd 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v56.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v65.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v65.lib.json
index d897646..b20a148 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v65.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v65.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v95.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v95.lib.json
index 3db27be..42d97c9 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v95.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ff_n40C_1v95.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_100C_1v60.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_100C_1v60.lib.json
index f233fbc..f1fafc2 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_100C_1v60.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_100C_1v60.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v28.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v28.lib.json
index bb8c4e2..ec905f1 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v28.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v44.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v44.lib.json
index c741dc7..76d1bc1 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v44.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v60.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v60.lib.json
index 140ee36..4cdd2b8 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v60.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v60.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v76.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v76.lib.json
index aead646..8340afb 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v76.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__tt_025C_1v80.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__tt_025C_1v80.lib.json
index 7c3e7d9..7eb82cc 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__tt_025C_1v80.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_1__tt_025C_1v80.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v65.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v65.lib.json
index 7614456..9166ac5 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v65.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v65.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v95.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v95.lib.json
index 0b33d5c..acd3765 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v95.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_100C_1v95.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v56.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v56.lib.json
index 628472d..3c60560 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v56.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v65.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v65.lib.json
index fea02a3..acf0dc9 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v65.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v65.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v95.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v95.lib.json
index 52519f5..af63dcf 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v95.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ff_n40C_1v95.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_100C_1v60.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_100C_1v60.lib.json
index b7d98be..a9e865a 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_100C_1v60.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_100C_1v60.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v28.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v28.lib.json
index aa919b4..d94de82 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v28.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v44.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v44.lib.json
index edb2785..52e0f3e 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v44.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v60.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v60.lib.json
index 5ba06ea..aabb2ec 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v60.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v60.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v76.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v76.lib.json
index cf2a0ab..0d2d6fa 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v76.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__tt_025C_1v80.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__tt_025C_1v80.lib.json
index 07e35b5..f28953d 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__tt_025C_1v80.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_2__tt_025C_1v80.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v65.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v65.lib.json
index 8523e88..a753ea4 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v65.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v65.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v95.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v95.lib.json
index 7afdd4b..5f4a344 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v95.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_100C_1v95.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v56.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v56.lib.json
index 516e7f1..1fcb87a 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v56.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v65.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v65.lib.json
index 7367566..07f4c41 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v65.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v65.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v95.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v95.lib.json
index 60c7283..6a31a72 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v95.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ff_n40C_1v95.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_100C_1v60.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_100C_1v60.lib.json
index 08eba16..0a15733 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_100C_1v60.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_100C_1v60.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v28.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v28.lib.json
index bfe30a6..5390174 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v28.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v44.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v44.lib.json
index e75f78a..1b798c1 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v44.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v60.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v60.lib.json
index 805c53e..19edfaf 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v60.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v60.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v76.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v76.lib.json
index 8eb7a70..75d2d78 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v76.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__tt_025C_1v80.lib.json b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__tt_025C_1v80.lib.json
index 754b646..8c3d8bb 100644
--- a/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__tt_025C_1v80.lib.json
+++ b/cells/a221oi/sky130_fd_sc_hdll__a221oi_4__tt_025C_1v80.lib.json
@@ -134,20 +134,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v65.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v65.lib.json
index ac59418..70ebfee 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v65.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v65.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v95.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v95.lib.json
index d692b73..14b01fe 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v95.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_100C_1v95.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v56.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v56.lib.json
index 9e11d59..01e4197 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v56.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v65.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v65.lib.json
index beae173..7130bbc 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v65.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v65.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v95.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v95.lib.json
index 46c3f7f..0854d46 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v95.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ff_n40C_1v95.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_100C_1v60.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_100C_1v60.lib.json
index 40f0412..23a01ad 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_100C_1v60.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_100C_1v60.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v28.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v28.lib.json
index fa527ab..3f4de88 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v28.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v44.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v44.lib.json
index b83877b..ba26cd6 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v44.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v60.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v60.lib.json
index 14fd43e..4963323 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v60.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v60.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v76.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v76.lib.json
index 3c25938..37cbf96 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v76.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__tt_025C_1v80.lib.json b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__tt_025C_1v80.lib.json
index 7b3ef35..75c2047 100644
--- a/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__tt_025C_1v80.lib.json
+++ b/cells/a222oi/sky130_fd_sc_hdll__a222oi_1__tt_025C_1v80.lib.json
@@ -262,20 +262,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v65.lib.json
index e91ed82..2e6eebc 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v95.lib.json
index 09afc5c..922277b 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v56.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v56.lib.json
index 52ff44d..d109095 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v56.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v65.lib.json
index fd0f675..716a9bc 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v95.lib.json
index 83e88a7..e3f25a5 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_100C_1v60.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_100C_1v60.lib.json
index 8cd7a81..49e4cbd 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_100C_1v60.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v28.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v28.lib.json
index acc5731..d258d22 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v28.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v44.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v44.lib.json
index 88058d4..ee9737b 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v44.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v60.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v60.lib.json
index 53483ba..f92612d 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v60.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v76.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v76.lib.json
index 551faf3..dd0f510 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v76.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_1__tt_025C_1v80.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_1__tt_025C_1v80.lib.json
index ef17d45..7b3f980 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_1__tt_025C_1v80.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_1__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v65.lib.json
index d4c7f45..cbf82e0 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v95.lib.json
index 5cb668b..a11edaa 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v56.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v56.lib.json
index 6ee0ca1..b21f1b0 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v56.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v65.lib.json
index 76cf2f4..1365bd5 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v95.lib.json
index e09fe29..6d8ffad 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_100C_1v60.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_100C_1v60.lib.json
index d8e1df8..7c76c87 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_100C_1v60.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v28.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v28.lib.json
index 8303605..72d23ad 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v28.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v44.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v44.lib.json
index 51a1011..1d3ffda 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v44.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v60.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v60.lib.json
index 6205e07..9a2b7a4 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v60.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v76.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v76.lib.json
index 780a7b4..49261d1 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v76.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_2__tt_025C_1v80.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_2__tt_025C_1v80.lib.json
index 8a2e684..0ca8958 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_2__tt_025C_1v80.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_2__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v65.lib.json
index 635f5fe..841140a 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v95.lib.json
index 52d5d33..5301a84 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v56.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v56.lib.json
index 1bdb7c6..20c3b1e 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v56.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v65.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v65.lib.json
index 9ea41f9..5b26a75 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v65.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v95.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v95.lib.json
index f76009c..c9873dc 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v95.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_100C_1v60.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_100C_1v60.lib.json
index 634bea9..47ef0e8 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_100C_1v60.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v28.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v28.lib.json
index 7e9b8e0..392664d 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v28.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v44.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v44.lib.json
index d270de9..0c6e5e7 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v44.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v60.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v60.lib.json
index 8983825..f3f9bf4 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v60.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v76.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v76.lib.json
index 118ce42..5d64e8e 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v76.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22o/sky130_fd_sc_hdll__a22o_4__tt_025C_1v80.lib.json b/cells/a22o/sky130_fd_sc_hdll__a22o_4__tt_025C_1v80.lib.json
index 4c4a584..bd0ed63 100644
--- a/cells/a22o/sky130_fd_sc_hdll__a22o_4__tt_025C_1v80.lib.json
+++ b/cells/a22o/sky130_fd_sc_hdll__a22o_4__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v65.lib.json
index a23771e..f116d9c 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v95.lib.json
index 72eb55b..9f61367 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v56.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v56.lib.json
index aedcde9..0d0636f 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v56.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v65.lib.json
index 1badd38..7d08732 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v95.lib.json
index 2a545a8..d626fc3 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_100C_1v60.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_100C_1v60.lib.json
index c9d085c..1053e0b 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_100C_1v60.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v28.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v28.lib.json
index 4effab7..86f53e7 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v28.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v44.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v44.lib.json
index a57de5c..7c14898 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v44.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v60.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v60.lib.json
index 31dead8..e5f2c09 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v60.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v76.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v76.lib.json
index af3ccfc..2fb85c1 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v76.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__tt_025C_1v80.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__tt_025C_1v80.lib.json
index f53b771..a4e14fc 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__tt_025C_1v80.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_1__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v65.lib.json
index efc0094..a9dae54 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v95.lib.json
index ba3ef5a..0ea642b 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v56.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v56.lib.json
index 5efd9dc..4445181 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v56.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v65.lib.json
index b87a964..9800d35 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v95.lib.json
index bbe8b64..ee09ff0 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_100C_1v60.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_100C_1v60.lib.json
index dbaedd8..dec657b 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_100C_1v60.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v28.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v28.lib.json
index bb0317d..c639d06 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v28.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v44.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v44.lib.json
index 00bf639..a7c9f39 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v44.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v60.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v60.lib.json
index 205da26..65dd19d 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v60.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v76.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v76.lib.json
index bcf24c6..b09fb63 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v76.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__tt_025C_1v80.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__tt_025C_1v80.lib.json
index 6246809..354bfbf 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__tt_025C_1v80.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_2__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v65.lib.json
index d191e6b..71af6ab 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v95.lib.json
index e2284c3..2e2981d 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v56.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v56.lib.json
index 866c77d..ae3ae81 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v56.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v65.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v65.lib.json
index bc7ad3f..9e5f6c1 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v65.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v95.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v95.lib.json
index d12201e..1e2a6f0 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v95.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_100C_1v60.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_100C_1v60.lib.json
index 08dc821..ef48b07 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_100C_1v60.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v28.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v28.lib.json
index 4e40e6d..24b804a 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v28.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v44.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v44.lib.json
index 8818e8b..0a95be6 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v44.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v60.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v60.lib.json
index c01bb28..f5f9439 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v60.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v76.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v76.lib.json
index a7443eb..acd2a1b 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v76.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__tt_025C_1v80.lib.json b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__tt_025C_1v80.lib.json
index db03925..e72d846 100644
--- a/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__tt_025C_1v80.lib.json
+++ b/cells/a22oi/sky130_fd_sc_hdll__a22oi_4__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v65.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v65.lib.json
index 3583196..4b6ea50 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v65.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v95.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v95.lib.json
index 73a6d9f..f57d660 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v95.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v56.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v56.lib.json
index 99680a2..59384dd 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v56.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v65.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v65.lib.json
index b63ac0e..7915614 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v65.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v95.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v95.lib.json
index 0b2cdcf..59a7eef 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v95.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_100C_1v60.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_100C_1v60.lib.json
index 59c6209..dc8e87f 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_100C_1v60.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v28.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v28.lib.json
index 10f35ba..ca57e12 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v28.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v44.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v44.lib.json
index 725a079..97c89e0 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v44.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v60.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v60.lib.json
index e52f062..ee0636b 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v60.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v76.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v76.lib.json
index c934493..9cd9d6a 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v76.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__tt_025C_1v80.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__tt_025C_1v80.lib.json
index cb1d637..d3d41ab 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__tt_025C_1v80.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_1__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v65.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v65.lib.json
index b2938f5..0ece6df 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v65.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v95.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v95.lib.json
index 7bc08ba..068f9b2 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v95.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v56.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v56.lib.json
index 2a67024..d7e6c97 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v56.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v65.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v65.lib.json
index 97f911f..52160b4 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v65.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v95.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v95.lib.json
index 1ef6fd8..f0fa2d2 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v95.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_100C_1v60.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_100C_1v60.lib.json
index 2412a59..641e8b0 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_100C_1v60.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v28.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v28.lib.json
index a4d6c28..2762e1c 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v28.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v44.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v44.lib.json
index 212950a..57ce493 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v44.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v60.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v60.lib.json
index 328cacc..e7bc99c 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v60.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v76.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v76.lib.json
index 3313518..0c214d9 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v76.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__tt_025C_1v80.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__tt_025C_1v80.lib.json
index 5c09cb4..5589213 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__tt_025C_1v80.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v65.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v65.lib.json
index b3d1972..248080d 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v65.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v95.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v95.lib.json
index 3b3783e..4cb34be 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v95.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v56.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v56.lib.json
index 8444f45..5ff5c50 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v56.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v65.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v65.lib.json
index da34879..e279630 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v65.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v95.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v95.lib.json
index 345fb31..aa531a7 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v95.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_100C_1v60.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_100C_1v60.lib.json
index d2d4591..a2b602a 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_100C_1v60.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v28.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v28.lib.json
index 461ada9..b0a894f 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v28.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v44.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v44.lib.json
index ea7c3f4..00c7858 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v44.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v60.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v60.lib.json
index 9e82d75..3f80779 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v60.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v76.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v76.lib.json
index 3de6fb4..41e1f47 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v76.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__tt_025C_1v80.lib.json b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__tt_025C_1v80.lib.json
index b72f29c..45a79d8 100644
--- a/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__tt_025C_1v80.lib.json
+++ b/cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_4__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v65.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v65.lib.json
index 069257f..2188d6f 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v65.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v95.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v95.lib.json
index 7e2b79a..156b114 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v95.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v56.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v56.lib.json
index 64ef2c7..b7fdf15 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v56.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v65.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v65.lib.json
index 302c38a..28f7419 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v65.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v95.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v95.lib.json
index 421a9a3..cb5fdb9 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v95.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_100C_1v60.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_100C_1v60.lib.json
index 9449f1d..573f7e4 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_100C_1v60.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v28.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v28.lib.json
index 4cfe193..c84a2e8 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v28.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v44.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v44.lib.json
index 0c6eda1..79dc65f 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v44.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v60.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v60.lib.json
index 5bc2690..7664bb0 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v60.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v76.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v76.lib.json
index ec2de0c..6781d6d 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v76.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__tt_025C_1v80.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__tt_025C_1v80.lib.json
index 58b4c8f..b8b56de 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__tt_025C_1v80.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v65.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v65.lib.json
index 1bff027..93219d0 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v65.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v95.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v95.lib.json
index 5043ffe..4741a7b 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v95.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v56.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v56.lib.json
index 5f03dbb..ca8565b 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v56.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v65.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v65.lib.json
index 1be9a57..140f43a 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v65.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v95.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v95.lib.json
index 70d904f..3fb4591 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v95.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_100C_1v60.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_100C_1v60.lib.json
index 0072292..d8761e7 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_100C_1v60.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v28.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v28.lib.json
index 7cfc34a..9271356 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v28.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v44.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v44.lib.json
index 39229a5..ca4ea36 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v44.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v60.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v60.lib.json
index a4c73aa..a8209c9 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v60.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v76.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v76.lib.json
index 52d4a32..1a30af1 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v76.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__ss_n40C_1v76.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__tt_025C_1v80.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__tt_025C_1v80.lib.json
index f3a9ac4..8178703 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__tt_025C_1v80.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_2__tt_025C_1v80.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v65.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v65.lib.json
index 72bd92f..ff22ce2 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v65.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v95.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v95.lib.json
index aa96785..9ba9ec7 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v95.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_100C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v56.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v56.lib.json
index d0ceffe..3f6e61b 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v56.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v56.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v65.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v65.lib.json
index f4bfb14..3f5ea1d 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v65.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v65.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v95.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v95.lib.json
index 4bd1fde..4c6ec67 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v95.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ff_n40C_1v95.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_100C_1v60.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_100C_1v60.lib.json
index f8d595a..ce351b2 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_100C_1v60.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_100C_1v60.lib.json
@@ -70,20 +70,22 @@
   ],
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v28.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v28.lib.json
index 477beae..87aaeaf 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v28.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v28.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {
diff --git a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v44.lib.json b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v44.lib.json
index 7e44e18..7ccb6d9 100644
--- a/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v44.lib.json
+++ b/cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4__ss_n40C_1v44.lib.json
@@ -4,20 +4,22 @@
   "cell_leakage_power": 0.0,
   "pg_pin,VGND": {
     "pg_type": "primary_ground",
-    "related_bias_pin": "VNB",
+    "related_bias_pin": "VPB",
     "voltage_name": "VGND"
   },
   "pg_pin,VNB": {
-    "pg_type": "pwell",
+    "pg_type": "nwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VNB"
   },
   "pg_pin,VPB": {
-    "pg_type": "nwell",
+    "pg_type": "pwell",
+    "physical_connection": "device_layer",
     "voltage_name": "VPB"
   },
   "pg_pin,VPWR": {
     "pg_type": "primary_power",
-    "related_bias_pin": "VPB",
+    "related_bias_pin": "VNB",
     "voltage_name": "VPWR"
   },
   "pin,A1_N": {