blob: 6383f21b88ffcfd6e4191bd0fa3654f6d4a81d36 [file] [log] [blame]
{
"area": 20.0192,
"cell_footprint": "sdlclkp",
"cell_leakage_power": 9.973405,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"leakage_power": [
{
"value": 12.2628,
"when": "CLK&!GATE&!GCLK&!SCE"
},
{
"value": 8.06815,
"when": "!CLK&GATE&!GCLK&!SCE"
},
{
"value": 8.03648,
"when": "!CLK&!GATE&!GCLK&SCE"
},
{
"value": 8.41307,
"when": "CLK&!GATE&GCLK&SCE"
},
{
"value": 7.19279,
"when": "!CLK&GATE&!GCLK&SCE"
},
{
"value": 10.377,
"when": "!CLK&!GATE&!GCLK&!SCE"
},
{
"value": 8.44477,
"when": "CLK&GATE&GCLK&!SCE"
},
{
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"when": "CLK&GATE&GCLK&SCE"
},
{
"value": 12.8314,
"when": "CLK&GATE&!GCLK&!SCE"
},
{
"value": 12.7997,
"when": "CLK&!GATE&!GCLK&SCE"
},
{
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"when": "CLK&GATE&!GCLK&SCE"
},
{
"value": 11.7292,
"when": "CLK&!GATE&GCLK&!SCE"
}
],
"pg_pin VGND": {
"pg_type": "primary_ground",
"related_bias_pin": "VNB",
"voltage_name": "VGND"
},
"pg_pin VNB": {
"pg_type": "pwell",
"voltage_name": "VNB"
},
"pg_pin VPB": {
"pg_type": "nwell",
"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"related_bias_pin": "VPB",
"voltage_name": "VPWR"
},
"pin CLK": {
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"clock": "true",
"clock_gate_clock_pin": "true",
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0.0531329,
0.122474,
0.282311,
0.650743,
1.5
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0.122474,
0.282311,
0.650743,
1.5
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0.0119439,
0.015585,
0.023978
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},
"max_transition": 1.5,
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"related_power_pin": "VPWR",
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}
},
"pin GATE": {
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"clock": "false",
"clock_gate_enable_pin": "true",
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"internal_power": {
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0.282311,
0.650743,
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0.0531329,
0.122474,
0.282311,
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0.0190032,
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0.3877422
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[
0.1019512,
0.2217266,
0.404832
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1.5
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0.01,
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1.5
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0.1204082,
0.100877
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[
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0.2192852,
0.2009746
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{
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0.5,
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[
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-0.3996113
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0.5,
1.5
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0.01,
0.5,
1.5
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-0.0468281
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[
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-0.0919941
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},
"sim_opt": "runlvl=5 accurate=1",
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}
]
},
"pin GCLK": {
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"direction": "output",
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0.0531329,
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0.650743,
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0.0531329,
0.122474,
0.282311,
0.650743,
1.5
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{
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{
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0.0230506,
0.0531329,
0.122474,
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{
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}
],
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"related_ground_pin": "VGND",
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"state_function": "(CLK*M0)",
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0.0230506,
0.0531329,
0.122474,
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[
-0.1040547,
-0.1957539,
-0.3471211
]
]
},
"related_pin": "CLK",
"rise_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.0456074,
-0.1006855,
-0.1006855
],
[
-0.0430195,
-0.0895527,
-0.088332
],
[
-0.0869648,
-0.133498,
-0.133498
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}