cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_1__ff_n40C_1v56.lib.json

{
  "area": 35.0336,
  "cell_footprint": "sdfrtp",
  "cell_leakage_power": 0.0,
  "ff IQ,IQ_N": {
    "clear": "!RESET_B",
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VNB",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002379,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002046,
    "internal_power": {
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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      "fall_constraint constraint_3_0_1": {
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      "rise_constraint constraint_3_0_1": {
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      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10.0
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  },
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    "capacitance": 0.001616,
    "clock": "false",
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        "fall_power scalar": {
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        "when": "(!D&RESET_B&SCD&SCE)"
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      {
        "fall_power scalar": {
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        "related_pin": "CLK",
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