| { |
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| "cell_footprint": "nor3b", |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
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| }, |
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| "voltage_name": "VPWR" |
| }, |
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| 0.0281727, |
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| }, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin C_N": { |
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| "clock": "false", |
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| }, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin Y": { |
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| "internal_power": [ |
| { |
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| ] |
| }, |
| "related_pin": "A", |
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| "when": "(!B&C_N)" |
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| { |
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| { |
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| "related_pin": "C_N", |
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| } |
| ], |
| "max_capacitance": 0.040636, |
| "max_transition": 4.998517, |
| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| 0.01, |
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