| { |
| "area": 11.2608, |
| "cell_footprint": "mux2", |
| "cell_leakage_power": 0.01920459, |
| "leakage_power": [ |
| { |
| "value": 0.0672975, |
| "when": "!A0&!A1&S" |
| }, |
| { |
| "value": 0.0666914, |
| "when": "!A0&!A1&!S" |
| }, |
| { |
| "value": 0.0024535, |
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| }, |
| { |
| "value": 0.004062, |
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| }, |
| { |
| "value": 0.0047116, |
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| }, |
| { |
| "value": 0.0018474, |
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| { |
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| }, |
| { |
| "value": 0.0029836, |
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| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "false", |
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| "fall_capacitance": 0.007391, |
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| 0.01, |
| 0.0230506, |
| 0.0531329, |
| 0.122474, |
| 0.282311, |
| 0.650743, |
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| 0.0142785, |
| 0.0143449, |
| 0.0144978 |
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| }, |
| "pin A1": { |
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| "fall_capacitance": 0.007375, |
| "internal_power": { |
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| 0.0230506, |
| 0.0531329, |
| 0.122474, |
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| 0.0144821, |
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| 0.0145956, |
| 0.0147781 |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.008487 |
| }, |
| "pin S": { |
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| "clock": "false", |
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| "fall_capacitance": 0.0113, |
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| 0.01, |
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| 0.0321564 |
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| "rise_power power_inputs_1": { |
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| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.012702 |
| }, |
| "pin X": { |
| "direction": "output", |
| "function": "(A0&!S) | (A1&S)", |
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| { |
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| }, |
| "related_pin": "A0", |
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| { |
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| }, |
| "related_pin": "A1", |
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| }, |
| { |
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| }, |
| "related_pin": "S", |
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| ], |
| "max_capacitance": 0.815058, |
| "max_transition": 1.50756, |
| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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