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| "enable": "!GATE_N" |
| }, |
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| "pg_type": "primary_ground", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "false", |
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| 0.0281727, |
| 0.0793701, |
| 0.223607, |
| 0.629961, |
| 1.77477, |
| 4.9999998 |
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| 0.0049391 |
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| "rise_power power_inputs_1": { |
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| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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| 5.0 |
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| [ |
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| ] |
| }, |
| "related_pin": "GATE_N", |
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| [ |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
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| }, |
| { |
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| 2.5, |
| 5.0 |
| ], |
| "index_2": [ |
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| [ |
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| }, |
| "related_pin": "GATE_N", |
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| 5.0 |
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| ] |
| }, |
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| "clock": "true", |
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| "related_pin": "GATE_N", |
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| "timing_type": "min_pulse_width", |
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| }, |
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| "direction": "output", |
| "function": "IQ", |
| "internal_power": [ |
| { |
| "fall_power scalar": { |
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| 0.0 |
| ] |
| }, |
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| { |
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| ], |
| "max_capacitance": 0.423441, |
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| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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