blob: f3b6a4fc30bdc95bc48e0e72ca6060846dcdad15 [file] [log] [blame]
{
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"cell_footprint": "dfstp",
"cell_leakage_power": 0.0,
"ff IQ,IQ_N": {
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"next_state": "D",
"preset": "!SET_B"
},
"pg_pin VGND": {
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"related_bias_pin": "VNB",
"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
"pg_pin VPB": {
"pg_type": "nwell",
"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"related_bias_pin": "VPB",
"voltage_name": "VPWR"
},
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0.0793701,
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}
},
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"clock": "false",
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0.223607,
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[
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1.0273907
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2.5,
5.0
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2.5,
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0.8711406
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{
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}
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"function": "IQ",
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{
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0.0793701,
0.223607,
0.629961,
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{
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0.223607,
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{
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}
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{
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0.223607,
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[
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[
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[
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[
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0.2048004,
0.4698047,
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5.9864615
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{
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1.3327908,
1.5631882,
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1.9527555,
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4.492871,
6.2743863
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0.0714517,
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{
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1.1388832,
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[
1.2030553,
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[
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[
1.955452,
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4.4935811,
6.2694627
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[
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[
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[
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[
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}
]
},
"pin SET_B": {
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"clock": "false",
"direction": "input",
"fall_capacitance": 0.002917,
"internal_power": {
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0.01,
0.0281727,
0.0793701,
0.223607,
0.629961,
1.77477,
4.9999998
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},
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0.0006266,
0.0005997,
0.000524,
0.0003107
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}
},
"max_transition": 5.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"rise_capacitance": 0.003028,
"timing": [
{
"related_pin": "CLK",
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0.01,
2.5,
5.0
],
"index_2": [
0.01,
2.5,
5.0
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0.1779277,
0.6387432
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[
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]
},
"sim_opt": "runlvl=5 accurate=1",
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"violation_delay_degrade_pct": 10.0
},
{
"related_pin": "CLK",
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0.01,
2.5,
5.0
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0.01,
2.5,
5.0
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"values": [
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0.5000469,
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0.3669902
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[
2.1255596,
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1.0804912
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]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "removal_rising",
"violation_delay_degrade_pct": 10.0
},
{
"fall_constraint constraint_3_0_1": {
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0.01,
2.5,
5.0
],
"values": [
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},
"related_pin": "SET_B",
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "min_pulse_width",
"violation_delay_degrade_pct": 10.0
}
]
}
}