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  "area": 13.7632,
  "cell_footprint": "and3b",
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    "pg_type": "primary_ground",
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    "voltage_name": "VGND"
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  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VPB",
    "voltage_name": "VPWR"
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    "max_transition": 1.5,
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    "clock": "false",
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    "internal_power": {
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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  "pin C": {
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    "clock": "false",
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    "internal_power": {
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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    "related_ground_pin": "VGND",
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