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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_hdll / 066893b8900b18848fd94956690eb15bcb7d0593 / . / cells / sedfxbp / sky130_fd_sc_hdll__sedfxbp_2__ss_n40C_1v76.lib.json
blob: ec9868f2908bf95e6a98fcfea715d3e1f2d286ea [file] [log] [blame]
{
"area": 45.0432,
"cell_footprint": "sedfxbp",
"cell_leakage_power": 0.0,
"ff IQ,IQ_N": {
"clocked_on": "CLK",
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"
},
"pg_pin VGND": {
"pg_type": "primary_ground",
"related_bias_pin": "VNB",
"voltage_name": "VGND"
},
"pg_pin VNB": {
"pg_type": "pwell",
"voltage_name": "VNB"
},
"pg_pin VPB": {
"pg_type": "nwell",
"voltage_name": "VPB"
},
"pg_pin VPWR": {
"pg_type": "primary_power",
"related_bias_pin": "VPB",
"voltage_name": "VPWR"
},
"pin CLK": {
"capacitance": 0.001679,
"clock": "true",
"direction": "input",
"fall_capacitance": 0.001514,
"internal_power": {
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0.01,
0.0230506,
0.0531329,
0.122474,
0.282311,
0.650743,
1.5
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0.0260987,
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"rise_power power_inputs_1": {
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"max_transition": 1.5,
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"timing": {
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0.01,
0.5,
1.5
],
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0.6353258,
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},
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0.01,
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],
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0.7836248,
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]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "min_pulse_width",
"violation_delay_degrade_pct": 10.0
}
},
"pin D": {
"capacitance": 0.001702,
"clock": "false",
"direction": "input",
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"internal_power": {
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0.0531329,
0.122474,
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{
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1.5
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0.01,
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1.5
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[
0.4413067,
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0.01,
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1.5
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0.01,
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1.5
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0.217918,
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0.1007305,
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},
{
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0.01,
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0.01,
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1.5
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[
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},
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0.01,
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1.5
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0.01,
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1.5
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},
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}
]
},
"pin DE": {
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"clock": "false",
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0.650743,
1.5
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{
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0.01,
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0.4901348,
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},
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},
{
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1.5
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},
"related_pin": "CLK",
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1.5
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0.01,
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1.5
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},
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}
]
},
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"function": "IQ",
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{
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},
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{
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{
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{
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0.059789,
0.0714111,
0.0950695,
0.1487348,
0.2679027,
0.5885906
],
[
0.0545966,
0.0597808,
0.0710821,
0.0948617,
0.1483167,
0.2679048,
0.5885216
],
[
0.0544095,
0.0600531,
0.0714299,
0.0948262,
0.1462402,
0.2676953,
0.5864079
],
[
0.0545703,
0.0598026,
0.0714128,
0.095084,
0.1477149,
0.2678436,
0.5887995
],
[
0.0544021,
0.0599282,
0.0709266,
0.0955106,
0.147536,
0.2681109,
0.5875666
]
]
},
"related_pin": "CLK",
"sdf_cond": "D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b1",
"timing_sense": "negative_unate",
"timing_type": "rising_edge",
"when": "(D&DE&SCD&SCE)"
}
]
},
"pin SCD": {
"capacitance": 0.001633,
"clock": "false",
"direction": "input",
"fall_capacitance": 0.001575,
"internal_power": {
"fall_power power_inputs_1": {
"index_1": [
0.01,
0.0230506,
0.0531329,
0.122474,
0.282311,
0.650743,
1.5
],
"values": [
0.0029368,
0.0029859,
0.0030991,
0.0030855,
0.0030543,
0.0029823,
0.0028162
]
},
"rise_power power_inputs_1": {
"index_1": [
0.01,
0.0230506,
0.0531329,
0.122474,
0.282311,
0.650743,
1.5
],
"values": [
-0.0028932,
-0.0029224,
-0.0029898,
-0.0030001,
-0.0030239,
-0.0030788,
-0.0032053
]
}
},
"max_transition": 1.5,
"nextstate_type": "scan_in",
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"rise_capacitance": 0.00169,
"timing": [
{
"fall_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
0.6111309,
0.7992656,
1.1776836
],
[
0.4254375,
0.6135723,
0.9895488
],
[
0.184959,
0.3706523,
0.7490703
]
]
},
"related_pin": "CLK",
"rise_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
0.1826641,
0.3268535,
0.5648906
],
[
0.0726543,
0.2180645,
0.4512188
],
[
-0.0506367,
0.092332,
0.326707
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "setup_rising",
"violation_delay_degrade_pct": 10.0
},
{
"fall_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.4472187,
-0.6341328,
-1.0125508
],
[
-0.2908223,
-0.4801777,
-0.857375
],
[
-0.0784199,
-0.2677754,
-0.6437519
]
]
},
"related_pin": "CLK",
"rise_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.1579121,
-0.3021015,
-0.5328145
],
[
-0.0515645,
-0.1957539,
-0.4264668
],
[
0.0705059,
-0.0675801,
-0.2995137
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"pin SCE": {
"capacitance": 0.002927,
"clock": "false",
"direction": "input",
"fall_capacitance": 0.002861,
"internal_power": {
"fall_power power_inputs_1": {
"index_1": [
0.01,
0.0230506,
0.0531329,
0.122474,
0.282311,
0.650743,
1.5
],
"values": [
0.0107432,
0.0106281,
0.0103627,
0.0103702,
0.0103875,
0.0104273,
0.0105191
]
},
"rise_power power_inputs_1": {
"index_1": [
0.01,
0.0230506,
0.0531329,
0.122474,
0.282311,
0.650743,
1.5
],
"values": [
0.0095405,
0.0093844,
0.0090246,
0.0090071,
0.0089666,
0.0088734,
0.0086586
]
}
},
"max_transition": 1.5,
"nextstate_type": "scan_enable",
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"rise_capacitance": 0.002993,
"timing": [
{
"fall_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
0.6306621,
0.8078105,
1.1776836
],
[
0.4461895,
0.6245586,
0.9944317
],
[
0.2008281,
0.3755351,
0.7466289
]
]
},
"related_pin": "CLK",
"rise_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
0.6233379,
0.7663066,
0.9311016
],
[
0.4376445,
0.5806133,
0.7478496
],
[
0.1959453,
0.3401348,
0.5061504
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "setup_rising",
"violation_delay_degrade_pct": 10.0
},
{
"fall_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.2836445,
-0.485207,
-0.8428731
],
[
-0.1772969,
-0.3788594,
-0.7365254
],
[
-0.0564473,
-0.2543477,
-0.6120137
]
]
},
"related_pin": "CLK",
"rise_constraint vio_3_3_1": {
"index_1": [
0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.142043,
-0.2972188,
-0.5279316
],
[
-0.0381367,
-0.1920918,
-0.4179219
],
[
0.0875957,
-0.0651387,
-0.2909688
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"test_cell": {
"ff IQ,IQ_N": {
"clocked_on": "CLK",
"next_state": "(D&DE) | (IQ&!DE)"
},
"pin CLK": {
"direction": "input"
},
"pin D": {
"direction": "input"
},
"pin DE": {
"direction": "input"
},
"pin Q": {
"direction": "output",
"function": "IQ",
"signal_type": "test_scan_out"
},
"pin Q_N": {
"direction": "output",
"function": "IQ_N",
"signal_type": "test_scan_out_inverted"
},
"pin SCD": {
"direction": "input",
"signal_type": "test_scan_in"
},
"pin SCE": {
"direction": "input",
"signal_type": "test_scan_enable"
}
}
}