blob: 764455e2ab612fdb093b7e115bf8eefe446fd494 [file] [log] [blame]
{
"area": 25.024,
"cell_footprint": "sdlclkp",
"cell_leakage_power": 12.36798,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"leakage_power": [
{
"value": 13.5038,
"when": "CLK&GATE&GCLK&!SCE"
},
{
"value": 12.6848,
"when": "CLK&GATE&GCLK&SCE"
},
{
"value": 13.8673,
"when": "CLK&GATE&!GCLK&!SCE"
},
{
"value": 13.8759,
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},
{
"value": 13.0483,
"when": "CLK&GATE&!GCLK&SCE"
},
{
"value": 16.8715,
"when": "CLK&!GATE&GCLK&!SCE"
},
{
"value": 13.3786,
"when": "CLK&!GATE&!GCLK&!SCE"
},
{
"value": 9.09218,
"when": "!CLK&GATE&!GCLK&!SCE"
},
{
"value": 9.10084,
"when": "!CLK&!GATE&!GCLK&SCE"
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{
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"when": "CLK&!GATE&GCLK&SCE"
},
{
"value": 8.27318,
"when": "!CLK&GATE&!GCLK&SCE"
},
{
"value": 11.2069,
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}
],
"pg_pin VGND": {
"pg_type": "primary_ground",
"related_bias_pin": "VNB",
"voltage_name": "VGND"
},
"pg_pin VNB": {
"pg_type": "pwell",
"voltage_name": "VNB"
},
"pg_pin VPB": {
"pg_type": "nwell",
"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"related_bias_pin": "VPB",
"voltage_name": "VPWR"
},
"pin CLK": {
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"clock": "true",
"clock_gate_clock_pin": "true",
"direction": "input",
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0.0230506,
0.0531329,
0.122474,
0.282311,
0.650743,
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0.282311,
0.650743,
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0.0226862
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}
},
"pin GATE": {
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"clock": "false",
"clock_gate_enable_pin": "true",
"direction": "input",
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"internal_power": {
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0.122474,
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0.650743,
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0.0531329,
0.122474,
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0.2082988,
0.3914043
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[
0.0995098,
0.2192852,
0.404832
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0.5,
1.5
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0.1436016
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0.263084,
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0.2900859
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{
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0.5,
1.5
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[
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-0.2116231,
-0.3959492
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0.5,
1.5
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0.01,
0.5,
1.5
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[
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-0.0919941
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},
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}
]
},
"pin GCLK": {
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"direction": "output",
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0.0531329,
0.122474,
0.282311,
0.650743,
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{
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0.3392076,
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{
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0.122474,
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{
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}
],
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"state_function": "(CLK*M0)",
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0.0230506,
0.0531329,
0.122474,
0.282311,
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1.5
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0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.0468281,
-0.103127,
-0.1043477
],
[
-0.0430195,
-0.0907734,
-0.0907734
],
[
-0.0857441,
-0.1322773,
-0.133498
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}