blob: 29374585c93e4a0b1c430e456e635536273b19d7 [file] [log] [blame]
{
"area": 20.0192,
"cell_footprint": "sdlclkp",
"cell_leakage_power": 6.519264,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"leakage_power": [
{
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"when": "CLK&!GATE&!GCLK&!SCE"
},
{
"value": 5.24819,
"when": "!CLK&GATE&!GCLK&!SCE"
},
{
"value": 5.25695,
"when": "!CLK&!GATE&!GCLK&SCE"
},
{
"value": 5.15765,
"when": "CLK&!GATE&GCLK&SCE"
},
{
"value": 4.76541,
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},
{
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},
{
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"when": "CLK&GATE&GCLK&!SCE"
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{
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{
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{
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{
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},
{
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}
],
"pg_pin VGND": {
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"related_bias_pin": "VNB",
"voltage_name": "VGND"
},
"pg_pin VNB": {
"pg_type": "pwell",
"voltage_name": "VNB"
},
"pg_pin VPB": {
"pg_type": "nwell",
"voltage_name": "VPB"
},
"pg_pin VPWR": {
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"related_bias_pin": "VPB",
"voltage_name": "VPWR"
},
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"clock": "true",
"clock_gate_clock_pin": "true",
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0.0531329,
0.122474,
0.282311,
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}
},
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"clock": "false",
"clock_gate_enable_pin": "true",
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0.2119609,
0.4145976
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0.2278301
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{
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[
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-0.409377
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1.5
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}
]
},
"pin GCLK": {
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{
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{
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0.01,
0.5,
1.5
],
"index_2": [
0.01,
0.5,
1.5
],
"values": [
[
-0.055373,
-0.1409688,
-0.1897969
],
[
-0.0320332,
-0.109084,
-0.15425
],
[
-0.0454609,
-0.121291,
-0.166457
]
]
},
"sim_opt": "runlvl=5 accurate=1",
"timing_type": "hold_rising",
"violation_delay_degrade_pct": 10.0
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}