)]}'
{
  "commit": "ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1",
  "tree": "0e596733cbcf8012cb083dacae362b0bec8feb5b",
  "parents": [
    "0f0b6a30675acbf8e3a23592acf8a5b91a747ff2",
    "28c101fc5db17bb6cadefa4c2a146693c685f1dc"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Tue Nov 10 09:01:03 2020 -0800"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Tue Nov 10 09:08:23 2020 -0800"
  },
  "message": "lpflow_bleeder: Fixing the verilog models.\n\nFixing both the functional and behavioural verilog models.\n\nFixes https://github.com/google/skywater-pdk/issues/154\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\nSigned-off-by: Tim Edwards \u003ctim@opencircuitdesign.com\u003e\n",
  "tree_diff": []
}