)]}'
{
  "commit": "0f0b6a30675acbf8e3a23592acf8a5b91a747ff2",
  "tree": "45505768d2dcfe28d2772a60e2260dc66e3724a5",
  "parents": [
    "28019fca60c8a65d4a37a3ec0db0b90a1fe26630",
    "25ed6683d31d66fc8e3d6bb157b300250a557edb"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Tue Nov 10 08:19:50 2020 -0800"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Tue Nov 10 08:50:45 2020 -0800"
  },
  "message": "verilog: Fixing spurious `wire 1\u0027b0` definition in lpflow_inputisolatch.\n\nFixes https://github.com/google/skywater-pdk/issues/178.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\nSigned-off-by: Tim Edwards \u003ctim@opencircuitdesign.com\u003e\n",
  "tree_diff": []
}