verilog: Fixing spurious `wire 1'b0` definition in lpflow_inputisolatch.

Fixes https://github.com/google/skywater-pdk/issues/178.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
Signed-off-by: Tim Edwards <tim@opencircuitdesign.com>

cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.functional.pp.v

diff --git a/cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.functional.pp.v b/cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.functional.pp.v
index a3e6eec..c61b7ad 100644
--- a/cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.functional.pp.v
+++ b/cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.functional.pp.v
@@ -54,7 +54,6 @@
 
     // Local signals
     wire buf_Q;
-    wire 1'b0 ;
 
     //                                     Name     Output  Other arguments
     sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D, SLEEP_B, 1'b0, VPWR, VGND);