)]}'
{
  "commit": "836b7fa01a1f7870ab44f6b59220b0ad7f6f0ebc",
  "tree": "65c282c590bce98221ea7015e5b9360532b7d3ba",
  "parents": [
    "9b8d061bb2dcdeaf367aacf4b592f6ca05df77df",
    "01fde9a432bc54094b017239f87c9f0aeae82947"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}