)]}'
{
  "commit": "9b8d061bb2dcdeaf367aacf4b592f6ca05df77df",
  "tree": "af2280258e58b833ecec11d442f56c7a6622a26f",
  "parents": [
    "c70c051bf1e4d7eecb28cf125ebf5465aaf86060",
    "23c9281bdb9d2bbcc75a2efa0b8077ec9f77fca6"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}