)]}'
{
  "commit": "01fde9a432bc54094b017239f87c9f0aeae82947",
  "tree": "d49d8b1f2be4d01d5ff80001cebbddb43ea856c1",
  "parents": [
    "23c9281bdb9d2bbcc75a2efa0b8077ec9f77fca6"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
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