Significant improvements to library sky130_fd_sc_hd version 0.0.1.

This commit contains major improvements to all files by regenerating
from original data, improving consistency and automated cross checking
of data.

These improvements should drastically reduce customer confusion when
using the library and further reduce future possibility for human errors to
creep into designs.

Notable improvements include;

 * A large number of files have been regenerated from original source
   data including most liberty timing files and spice simulation models
   (compared to previous hand created versions).

 * Catalog and other library aggregations are now automatically
   generated from library contents (compared to previous hand created
   versions).

 * Significant improvements to documentation for all cells, including
   producing graphical representations, verified metadata and
   descriptions.

 * Names have been cross referenced between file types (such as
   simulation, layout, schematic and timing) and now verified to match.

 * Names have been improved to fix a standard format across all supported
   libraries and PDK contents.

 * Significant improvements to the contents of text files (like the
   verilog files) through improving consistent style that has been
   automatically checked.

 * Simplified verilog files for usage with open tools, including new
   black box stubs have been created.

 * Too many numerous other changes to list here.

Signed-off-by: Kevin Kelley <kevin.kelley@skywatertechnology.com>
diff --git a/README.rst b/README.rst
index 479c4c2..8d0e1b9 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,5 @@
 :lib:`sky130_fd_sc_hd` - SKY130 High Density Digital Standard Cells (SkyWater Provided)
 =======================================================================================
 
-Initial empty repository creation.
+Initial release of version (0, 0, 1).
 
diff --git a/cells/a2111o/definition.json b/cells/a2111o/definition.json
new file mode 100644
index 0000000..da45633
--- /dev/null
+++ b/cells/a2111o/definition.json
@@ -0,0 +1,72 @@
+{
+ "description": "2-input AND into first input of 4-input OR.",
+ "equation": "X = ((A1 & A2) | B1 | C1 | D1)",
+ "file_prefix": "sky130_fd_sc_hd__a2111o",
+ "library": "sky130_fd_sc_hd",
+ "name": "a2111o",
+ "parameters": [],
+ "ports": [
+  [
+   "signal",
+   "X",
+   "output",
+   ""
+  ],
+  [
+   "signal",
+   "A1",
+   "input",
+   ""
+  ],
+  [
+   "signal",
+   "A2",
+   "input",
+   ""
+  ],
+  [
+   "signal",
+   "B1",
+   "input",
+   ""
+  ],
+  [
+   "signal",
+   "C1",
+   "input",
+   ""
+  ],
+  [
+   "signal",
+   "D1",
+   "input",
+   ""
+  ],
+  [
+   "power",
+   "VPWR",
+   "input",
+   "supply1"
+  ],
+  [
+   "power",
+   "VGND",
+   "input",
+   "supply0"
+  ],
+  [
+   "power",
+   "VPB",
+   "input",
+   "supply1"
+  ],
+  [
+   "power",
+   "VNB",
+   "input",
+   "supply0"
+  ]
+ ],
+ "type": "cell",
+ "verilog_name": "sky130_fd_sc_hd__a2111o"
+}
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.pp.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.pp.v
new file mode 100644
index 0000000..95c207b
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.pp.v
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , C1, B1, and0_out, D1 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.v
new file mode 100644
index 0000000..e083cb1
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.v
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2              );
+    or  or0  (or0_out_X, C1, B1, and0_out, D1);
+    buf buf0 (X        , or0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.blackbox.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.blackbox.v
new file mode 100644
index 0000000..2c7b0c2
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.blackbox.v
@@ -0,0 +1,61 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_BLACKBOX_V
+`define SKY130_FD_SC_HD__A2111O_BLACKBOX_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hd__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_BLACKBOX_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.functional.pp.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.functional.pp.v
new file mode 100644
index 0000000..7856e6b
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.functional.pp.v
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , C1, B1, and0_out, D1 );
+    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v
new file mode 100644
index 0000000..b42a523
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hd__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2              );
+    or  or0  (or0_out_X, C1, B1, and0_out, D1);
+    buf buf0 (X        , or0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.json b/cells/a2111o/sky130_fd_sc_hd__a2111o.json
new file mode 100644
index 0000000..8a5abe7
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.json
@@ -0,0 +1,207 @@
+{
+  "creator": "Yosys 0.9+2406 (git sha1 46ed0db2, clang 7.0.1-8 -fPIC -Os)",
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+        }
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+          "attributes": {
+            "src": "./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:53.10-53.18"
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+          "bits": [ 2 ],
+          "attributes": {
+            "src": "./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:54.10-54.19"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.blackbox.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.blackbox.v
new file mode 100644
index 0000000..89c1ba5
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.blackbox.v
@@ -0,0 +1,62 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_PP_BLACKBOX_V
+`define SKY130_FD_SC_HD__A2111O_PP_BLACKBOX_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hd__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_PP_BLACKBOX_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.svg b/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.svg
new file mode 100644
index 0000000..23b262f
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.svg
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created by Symbolator http://kevinpt.github.io/symbolator -->
+<svg xmlns="http://www.w3.org/2000/svg"
+xmlns:xlink="http://www.w3.org/1999/xlink"
+xml:space="preserve"
+width="191" height="339" viewBox="-25 -56 191.0 339.0" version="1.1">
+<style type="text/css">
+<![CDATA[
+.fnt1 { fill:#000000; font-family:Times; font-size:12pt; font-weight:normal; font-style:italic; }
+.fnt2 { fill:#000000; font-family:Helvetica; font-size:12pt; font-weight:normal; font-style:normal; }
+.fnt3 { fill:#000000; font-family:Helvetica; font-size:16pt; font-weight:bold; font-style:normal; }
+.fnt4 { fill:#000000; font-family:Helvetica; font-size:10pt; font-style:normal; }
+.label {fill:#000;
+  text-anchor:middle;
+  font-size:16pt; font-weight:bold; font-family:Sans;}
+.link {fill: #0D47A1;}
+.link:hover {fill: #0D47A1; text-decoration:underline;}
+.link:visited {fill: #4A148C;}
+]]>
+</style>
+<defs>
+
+</defs>
+<rect x="-25" y="-56" width="100%" height="100%" fill="white"/><g transform="translate(0,0)">
+<rect x="0" y="-21.0" width="140" height="149.0" stroke="#000000" fill="#CCFED2" stroke-width="1"/>
+<text class="fnt1" x="70.0" y="-5.0" text-anchor="middle" dy="5.5">Data Signals</text>
+<g transform="translate(0,19)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">A1</text>
+</g>
+<g transform="translate(0,41)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">A2</text>
+</g>
+<g transform="translate(0,63)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">B1</text>
+</g>
+<g transform="translate(0,85)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">C1</text>
+</g>
+<g transform="translate(0,107)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">D1</text>
+</g>
+<g transform="translate(140,19)">
+<line x1="20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="-10" y="0" text-anchor="end" dy="5.5">X</text>
+</g>
+</g>
+<g transform="translate(0,149.0)">
+<rect x="0" y="-21.0" width="140" height="127.0" stroke="#000000" fill="#FFBBBB" stroke-width="1"/>
+<text class="fnt1" x="70.0" y="-5.0" text-anchor="middle" dy="5.5">Power</text>
+<g transform="translate(0,19)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VPB</text>
+</g>
+<g transform="translate(0,41)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VPWR</text>
+</g>
+<g transform="translate(0,63)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VGND</text>
+</g>
+<g transform="translate(0,85)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">VNB</text>
+</g>
+</g>
+<rect x="1.0" y="-20.0" width="138.0" height="274.0" stroke="#000000" fill="none" stroke-width="3"/>
+<text class="fnt3" x="70.0" y="-30.0" text-anchor="middle" dy="-1.0">a2111o</text>
+<text class="fnt4" x="70.0" y="274.0" text-anchor="middle" dy="1.0">sky130_fd_sc_hd</text>
+</svg>
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.v
new file mode 100644
index 0000000..2aaeb8f
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.pp.symbol.v
@@ -0,0 +1,55 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_PP_SYMBOL_V
+`define SKY130_FD_SC_HD__A2111O_PP_SYMBOL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hd__a2111o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    input  D1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_PP_SYMBOL_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.schematic.svg b/cells/a2111o/sky130_fd_sc_hd__a2111o.schematic.svg
new file mode 100644
index 0000000..21415db
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.schematic.svg
@@ -0,0 +1,114 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="314" height="249">
+  <style>svg {
+    stroke:#000;
+    fill:none;
+  }
+  text {
+    fill:#000;
+    stroke:none;
+    font-size:10px;
+    font-weight: bold;
+    font-family: "Courier New", monospace;
+  }
+  .nodelabel {
+    text-anchor: middle;
+  }
+  .inputPortLabel {
+    text-anchor: end;
+  }
+  .splitjoinBody {
+    fill:#000;
+  }</style>
+  <g s:type="and" transform="translate(77,157)" s:width="30" s:height="25" id="cell_$and$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:57$1">
+    <s:alias val="$and"/>
+    <s:alias val="$logic_and"/>
+    <s:alias val="$_AND_"/>
+    <path d="M0,0 L0,25 L15,25 A15 12.5 0 0 0 15,0 Z" class="cell_$and$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:57$1"/>
+    <g s:x="0" s:y="5" s:pid="A"/>
+    <g s:x="0" s:y="20" s:pid="B"/>
+    <g s:x="30" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="or" transform="translate(77,27)" s:width="30" s:height="25" id="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$2">
+    <s:alias val="$or"/>
+    <s:alias val="$logic_or"/>
+    <s:alias val="$_OR_"/>
+    <path d="M0,25 L0,25 L15,25 A15 12.5 0 0 0 15,0 L0,0" class="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$2"/>
+    <path d="M0,0 A30 25 0 0 1 0,25" class="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$2"/>
+    <g s:x="3" s:y="5" s:pid="A"/>
+    <g s:x="3" s:y="20" s:pid="B"/>
+    <g s:x="30" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="or" transform="translate(142,34.5)" s:width="30" s:height="25" id="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$3">
+    <s:alias val="$or"/>
+    <s:alias val="$logic_or"/>
+    <s:alias val="$_OR_"/>
+    <path d="M0,25 L0,25 L15,25 A15 12.5 0 0 0 15,0 L0,0" class="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$3"/>
+    <path d="M0,0 A30 25 0 0 1 0,25" class="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$3"/>
+    <g s:x="3" s:y="5" s:pid="A"/>
+    <g s:x="3" s:y="20" s:pid="B"/>
+    <g s:x="30" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="or" transform="translate(207,42)" s:width="30" s:height="25" id="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$4">
+    <s:alias val="$or"/>
+    <s:alias val="$logic_or"/>
+    <s:alias val="$_OR_"/>
+    <path d="M0,25 L0,25 L15,25 A15 12.5 0 0 0 15,0 L0,0" class="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$4"/>
+    <path d="M0,0 A30 25 0 0 1 0,25" class="cell_$or$./cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v:58$4"/>
+    <g s:x="3" s:y="5" s:pid="A"/>
+    <g s:x="3" s:y="20" s:pid="B"/>
+    <g s:x="30" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="outputExt" transform="translate(272,44.5)" s:width="30" s:height="20" id="cell_X">
+    <text x="15" y="-4" class="nodelabel cell_X" s:attribute="ref">X</text>
+    <s:alias val="$_outputExt_"/>
+    <path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_X"/>
+    <g s:x="0" s:y="10" s:pid="A"/>
+  </g>
+  <g s:type="inputExt" transform="translate(12,152)" s:width="30" s:height="20" id="cell_A1">
+    <text x="15" y="-4" class="nodelabel cell_A1" s:attribute="ref">A1</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A1"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <g s:type="inputExt" transform="translate(12,217)" s:width="30" s:height="20" id="cell_A2">
+    <text x="15" y="-4" class="nodelabel cell_A2" s:attribute="ref">A2</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_A2"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <g s:type="inputExt" transform="translate(12,87)" s:width="30" s:height="20" id="cell_B1">
+    <text x="15" y="-4" class="nodelabel cell_B1" s:attribute="ref">B1</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_B1"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <g s:type="inputExt" transform="translate(12,22)" s:width="30" s:height="20" id="cell_C1">
+    <text x="15" y="-4" class="nodelabel cell_C1" s:attribute="ref">C1</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_C1"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <g s:type="inputExt" transform="translate(142,104.5)" s:width="30" s:height="20" id="cell_D1">
+    <text x="15" y="-4" class="nodelabel cell_D1" s:attribute="ref">D1</text>
+    <s:alias val="$_inputExt_"/>
+    <path d="M0,0 L0,20 L15,20 L30,10 L15,0 Z" class="cell_D1"/>
+    <g s:x="28" s:y="10" s:pid="Y"/>
+  </g>
+  <line x1="40" x2="77" y1="162" y2="162" class="net_3"/>
+  <line x1="40" x2="52" y1="227" y2="227" class="net_4"/>
+  <line x1="52" x2="52" y1="227" y2="177" class="net_4"/>
+  <line x1="52" x2="77" y1="177" y2="177" class="net_4"/>
+  <line x1="40" x2="80" y1="32" y2="32" class="net_6"/>
+  <line x1="40" x2="52" y1="97" y2="97" class="net_5"/>
+  <line x1="52" x2="52" y1="97" y2="47" class="net_5"/>
+  <line x1="52" x2="80" y1="47" y2="47" class="net_5"/>
+  <line x1="107" x2="145" y1="39.5" y2="39.5" class="net_9"/>
+  <line x1="107" x2="117" y1="169.5" y2="169.5" class="net_8"/>
+  <line x1="117" x2="117" y1="169.5" y2="54.5" class="net_8"/>
+  <line x1="117" x2="145" y1="54.5" y2="54.5" class="net_8"/>
+  <line x1="172" x2="210" y1="47" y2="47" class="net_10"/>
+  <line x1="170" x2="182" y1="114.5" y2="114.5" class="net_7"/>
+  <line x1="182" x2="182" y1="114.5" y2="62" class="net_7"/>
+  <line x1="182" x2="210" y1="62" y2="62" class="net_7"/>
+  <line x1="237" x2="272" y1="54.5" y2="54.5" class="net_2"/>
+</svg>
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.specify.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.specify.v
new file mode 100644
index 0000000..30d6e9d
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.specify.v
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0);
+endspecify
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.svg b/cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.svg
new file mode 100644
index 0000000..1c0813f
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.svg
@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created by Symbolator http://kevinpt.github.io/symbolator -->
+<svg xmlns="http://www.w3.org/2000/svg"
+xmlns:xlink="http://www.w3.org/1999/xlink"
+xml:space="preserve"
+width="191" height="212" viewBox="-25 -56 191.0 212.0" version="1.1">
+<style type="text/css">
+<![CDATA[
+.fnt1 { fill:#000000; font-family:Times; font-size:12pt; font-weight:normal; font-style:italic; }
+.fnt2 { fill:#000000; font-family:Helvetica; font-size:12pt; font-weight:normal; font-style:normal; }
+.fnt3 { fill:#000000; font-family:Helvetica; font-size:16pt; font-weight:bold; font-style:normal; }
+.fnt4 { fill:#000000; font-family:Helvetica; font-size:10pt; font-style:normal; }
+.label {fill:#000;
+  text-anchor:middle;
+  font-size:16pt; font-weight:bold; font-family:Sans;}
+.link {fill: #0D47A1;}
+.link:hover {fill: #0D47A1; text-decoration:underline;}
+.link:visited {fill: #4A148C;}
+]]>
+</style>
+<defs>
+
+</defs>
+<rect x="-25" y="-56" width="100%" height="100%" fill="white"/><g transform="translate(0,0)">
+<rect x="0" y="-21.0" width="140" height="149.0" stroke="#000000" fill="#CCFED2" stroke-width="1"/>
+<text class="fnt1" x="70.0" y="-5.0" text-anchor="middle" dy="5.5">Data Signals</text>
+<g transform="translate(0,19)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">A1</text>
+</g>
+<g transform="translate(0,41)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">A2</text>
+</g>
+<g transform="translate(0,63)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">B1</text>
+</g>
+<g transform="translate(0,85)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">C1</text>
+</g>
+<g transform="translate(0,107)">
+<line x1="-20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="10" y="0" text-anchor="normal" dy="5.5">D1</text>
+</g>
+<g transform="translate(140,19)">
+<line x1="20" y1="0" x2="0" y2="0" stroke="#000000" fill="none" stroke-width="1"/>
+<text class="fnt2" x="-10" y="0" text-anchor="end" dy="5.5">X</text>
+</g>
+</g>
+<rect x="1.0" y="-20.0" width="138.0" height="147.0" stroke="#000000" fill="none" stroke-width="3"/>
+<text class="fnt3" x="70.0" y="-30.0" text-anchor="middle" dy="-1.0">a2111o</text>
+<text class="fnt4" x="70.0" y="147.0" text-anchor="middle" dy="1.0">sky130_fd_sc_hd</text>
+</svg>
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.v
new file mode 100644
index 0000000..639fcf1
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.symbol.v
@@ -0,0 +1,56 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_SYMBOL_V
+`define SKY130_FD_SC_HD__A2111O_SYMBOL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hd__a2111o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    input  D1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_SYMBOL_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.tb.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.tb.v
new file mode 100644
index 0000000..8dfe2d1
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.tb.v
@@ -0,0 +1,118 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_TB_V
+`define SKY130_FD_SC_HD__A2111O_TB_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include "sky130_fd_sc_hd__a2111o.v"
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg D1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1'bX;
+        A2   = 1'bX;
+        B1   = 1'bX;
+        C1   = 1'bX;
+        D1   = 1'bX;
+        VGND = 1'bX;
+        VNB  = 1'bX;
+        VPB  = 1'bX;
+        VPWR = 1'bX;
+
+        #20   A1   = 1'b0;
+        #40   A2   = 1'b0;
+        #60   B1   = 1'b0;
+        #80   C1   = 1'b0;
+        #100  D1   = 1'b0;
+        #120  VGND = 1'b0;
+        #140  VNB  = 1'b0;
+        #160  VPB  = 1'b0;
+        #180  VPWR = 1'b0;
+        #200  A1   = 1'b1;
+        #220  A2   = 1'b1;
+        #240  B1   = 1'b1;
+        #260  C1   = 1'b1;
+        #280  D1   = 1'b1;
+        #300  VGND = 1'b1;
+        #320  VNB  = 1'b1;
+        #340  VPB  = 1'b1;
+        #360  VPWR = 1'b1;
+        #380  A1   = 1'b0;
+        #400  A2   = 1'b0;
+        #420  B1   = 1'b0;
+        #440  C1   = 1'b0;
+        #460  D1   = 1'b0;
+        #480  VGND = 1'b0;
+        #500  VNB  = 1'b0;
+        #520  VPB  = 1'b0;
+        #540  VPWR = 1'b0;
+        #560  VPWR = 1'b1;
+        #580  VPB  = 1'b1;
+        #600  VNB  = 1'b1;
+        #620  VGND = 1'b1;
+        #640  D1   = 1'b1;
+        #660  C1   = 1'b1;
+        #680  B1   = 1'b1;
+        #700  A2   = 1'b1;
+        #720  A1   = 1'b1;
+        #740  VPWR = 1'bx;
+        #760  VPB  = 1'bx;
+        #780  VNB  = 1'bx;
+        #800  VGND = 1'bx;
+        #820  D1   = 1'bx;
+        #840  C1   = 1'bx;
+        #860  B1   = 1'bx;
+        #880  A2   = 1'bx;
+        #900  A1   = 1'bx;
+    end
+
+    sky130_fd_sc_hd__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_TB_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o.v b/cells/a2111o/sky130_fd_sc_hd__a2111o.v
new file mode 100644
index 0000000..5bca548
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o.v
@@ -0,0 +1,54 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_V
+`define SKY130_FD_SC_HD__A2111O_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include "sky130_fd_sc_hd__a2111o.pp.functional.v"
+`else  // FUNCTIONAL
+`include "sky130_fd_sc_hd__a2111o.pp.behavioral.v"
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include "sky130_fd_sc_hd__a2111o.functional.v"
+`else  // FUNCTIONAL
+`include "sky130_fd_sc_hd__a2111o.behavioral.v"
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.cdl b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.cdl
new file mode 100644
index 0000000..2750e77
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.cdl
@@ -0,0 +1,43 @@
+* Copyright 2020 The SkyWater PDK Authors
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+
+.SUBCKT sky130_fd_sc_hd__a2111o_1 A1 A2 B1 C1 D1 VGND VNB VPB VPWR X
+*.PININFO A1:I A2:I B1:I C1:I D1:I VGND:I VNB:I VPB:I VPWR:I X:O
+MMPA0 pndA A1 VPB phighvt m=1 w=1.0 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMPA1 pndA A2 VPB phighvt m=1 w=1.0 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMPB0 pndB B1 VPB phighvt m=1 w=1.0 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMPC0 pndC C1 VPB phighvt m=1 w=1.0 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMPD0 y D1 VPB phighvt m=1 w=1.0 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMIPX X y VPB phighvt m=1 w=1.0 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMNA0 y A1 VNB nshort m=1 w=0.65 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMNA1 sndA1 A2 VNB nshort m=1 w=0.65 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMNB0 y B1 VNB nshort m=1 w=0.65 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMNC0 y C1 VNB nshort m=1 w=0.65 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMND0 y D1 VNB nshort m=1 w=0.65 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+MMINX X y VNB nshort m=1 w=0.65 l=0.15 mult=1 sa=0.265 sb=0.265
++ sd=0.28 topography=normal area=0.063 perim=1.14
+.ENDS sky130_fd_sc_hd__a2111o_1
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.gds b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.gds
new file mode 100644
index 0000000..b4d1193
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.gds
Binary files differ
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.lef b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.lef
new file mode 100644
index 0000000..eb0f9b4
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.lef
@@ -0,0 +1,130 @@
+# Copyright 2020 The SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+VERSION 5.5 ;
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+MACRO sky130_fd_sc_hd__a2111o_1
+  CLASS CORE ;
+  SOURCE USER ;
+  ORIGIN  0.000000  0.000000 ;
+  SIZE  4.140000 BY  2.720000 ;
+  SYMMETRY X Y R90 ;
+  SITE unithd ;
+  PIN A1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 2.905000 0.995000 3.290000 1.325000 ;
+        RECT 2.985000 0.285000 3.540000 0.845000 ;
+        RECT 2.985000 0.845000 3.290000 0.995000 ;
+    END
+  END A1
+  PIN A2
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 3.510000 1.025000 4.010000 1.290000 ;
+    END
+  END A2
+  PIN B1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 2.400000 0.995000 2.680000 2.465000 ;
+    END
+  END B1
+  PIN C1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 1.890000 1.050000 2.220000 2.465000 ;
+    END
+  END C1
+  PIN D1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 1.290000 1.050000 1.720000 1.290000 ;
+        RECT 1.515000 1.290000 1.720000 2.465000 ;
+    END
+  END D1
+  PIN X
+    ANTENNADIFFAREA  0.504500 ;
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 0.135000 0.255000 0.465000 1.620000 ;
+        RECT 0.135000 1.620000 0.390000 2.460000 ;
+    END
+  END X
+  PIN VGND
+    DIRECTION INOUT ;
+    SHAPE ABUTMENT ;
+    USE GROUND ;
+    PORT
+      LAYER li1 ;
+        RECT 0.000000 -0.085000 4.140000 0.085000 ;
+        RECT 0.635000  0.085000 1.310000 0.470000 ;
+        RECT 2.085000  0.085000 2.430000 0.485000 ;
+        RECT 3.715000  0.085000 3.955000 0.760000 ;
+    END
+    PORT
+      LAYER met1 ;
+        RECT 0.000000 -0.240000 4.140000 0.240000 ;
+    END
+  END VGND
+  PIN VPWR
+    DIRECTION INOUT ;
+    SHAPE ABUTMENT ;
+    USE POWER ;
+    PORT
+      LAYER li1 ;
+        RECT 0.000000 2.635000 4.140000 2.805000 ;
+        RECT 0.565000 1.815000 0.895000 2.635000 ;
+        RECT 3.325000 1.835000 3.540000 2.635000 ;
+    END
+    PORT
+      LAYER met1 ;
+        RECT 0.000000 2.480000 4.140000 2.960000 ;
+    END
+  END VPWR
+  OBS
+    LAYER li1 ;
+      RECT 0.695000 0.650000 1.915000 0.655000 ;
+      RECT 0.695000 0.655000 2.805000 0.825000 ;
+      RECT 0.695000 0.825000 0.915000 1.465000 ;
+      RECT 0.695000 1.465000 1.345000 1.645000 ;
+      RECT 1.135000 1.645000 1.345000 2.460000 ;
+      RECT 1.585000 0.260000 1.915000 0.650000 ;
+      RECT 2.600000 0.260000 2.805000 0.655000 ;
+      RECT 2.860000 1.495000 3.990000 1.665000 ;
+      RECT 2.860000 1.665000 3.145000 2.460000 ;
+      RECT 3.720000 1.665000 3.990000 2.460000 ;
+  END
+END sky130_fd_sc_hd__a2111o_1
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.magic.lef b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.magic.lef
new file mode 100644
index 0000000..e892626
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.magic.lef
@@ -0,0 +1,151 @@
+# Copyright 2020 The SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+VERSION 5.7 ;
+  NAMESCASESENSITIVE ON ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+UNITS
+  DATABASE MICRONS 200 ;
+END UNITS
+MACRO sky130_fd_sc_hd__a2111o_1
+  CLASS CORE ;
+  SOURCE USER ;
+  FOREIGN sky130_fd_sc_hd__a2111o_1 ;
+  ORIGIN  0.000000  0.000000 ;
+  SIZE  4.140000 BY  2.720000 ;
+  SYMMETRY X Y R90 ;
+  SITE unithd ;
+  PIN A1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 2.905000 0.995000 3.290000 1.325000 ;
+        RECT 2.985000 0.285000 3.540000 0.845000 ;
+        RECT 2.985000 0.845000 3.290000 0.995000 ;
+    END
+  END A1
+  PIN A2
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 3.510000 1.025000 4.010000 1.290000 ;
+    END
+  END A2
+  PIN B1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 2.400000 0.995000 2.680000 2.465000 ;
+    END
+  END B1
+  PIN C1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 1.890000 1.050000 2.220000 2.465000 ;
+    END
+  END C1
+  PIN D1
+    ANTENNAGATEAREA  0.247500 ;
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 1.290000 1.050000 1.720000 1.290000 ;
+        RECT 1.515000 1.290000 1.720000 2.465000 ;
+    END
+  END D1
+  PIN X
+    ANTENNADIFFAREA  0.504500 ;
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER li1 ;
+        RECT 0.135000 0.255000 0.465000 1.620000 ;
+        RECT 0.135000 1.620000 0.390000 2.460000 ;
+    END
+  END X
+  PIN VGND
+    DIRECTION INOUT ;
+    SHAPE ABUTMENT ;
+    USE GROUND ;
+    PORT
+      LAYER li1 ;
+        RECT 0.000000 -0.085000 4.140000 0.085000 ;
+        RECT 0.635000  0.085000 1.310000 0.470000 ;
+        RECT 2.085000  0.085000 2.430000 0.485000 ;
+        RECT 3.715000  0.085000 3.955000 0.760000 ;
+      LAYER mcon ;
+        RECT 0.145000 -0.085000 0.315000 0.085000 ;
+        RECT 0.605000 -0.085000 0.775000 0.085000 ;
+        RECT 1.065000 -0.085000 1.235000 0.085000 ;
+        RECT 1.525000 -0.085000 1.695000 0.085000 ;
+        RECT 1.985000 -0.085000 2.155000 0.085000 ;
+        RECT 2.445000 -0.085000 2.615000 0.085000 ;
+        RECT 2.905000 -0.085000 3.075000 0.085000 ;
+        RECT 3.365000 -0.085000 3.535000 0.085000 ;
+        RECT 3.825000 -0.085000 3.995000 0.085000 ;
+      LAYER met1 ;
+        RECT 0.000000 -0.240000 4.140000 0.240000 ;
+    END
+  END VGND
+  PIN VPWR
+    DIRECTION INOUT ;
+    SHAPE ABUTMENT ;
+    USE POWER ;
+    PORT
+      LAYER li1 ;
+        RECT 0.000000 2.635000 4.140000 2.805000 ;
+        RECT 0.565000 1.815000 0.895000 2.635000 ;
+        RECT 3.325000 1.835000 3.540000 2.635000 ;
+      LAYER mcon ;
+        RECT 0.145000 2.635000 0.315000 2.805000 ;
+        RECT 0.605000 2.635000 0.775000 2.805000 ;
+        RECT 1.065000 2.635000 1.235000 2.805000 ;
+        RECT 1.525000 2.635000 1.695000 2.805000 ;
+        RECT 1.985000 2.635000 2.155000 2.805000 ;
+        RECT 2.445000 2.635000 2.615000 2.805000 ;
+        RECT 2.905000 2.635000 3.075000 2.805000 ;
+        RECT 3.365000 2.635000 3.535000 2.805000 ;
+        RECT 3.825000 2.635000 3.995000 2.805000 ;
+      LAYER met1 ;
+        RECT 0.000000 2.480000 4.140000 2.960000 ;
+    END
+  END VPWR
+  OBS
+    LAYER li1 ;
+      RECT 0.695000 0.650000 1.915000 0.655000 ;
+      RECT 0.695000 0.655000 2.805000 0.825000 ;
+      RECT 0.695000 0.825000 0.915000 1.465000 ;
+      RECT 0.695000 1.465000 1.345000 1.645000 ;
+      RECT 1.135000 1.645000 1.345000 2.460000 ;
+      RECT 1.585000 0.260000 1.915000 0.650000 ;
+      RECT 2.600000 0.260000 2.805000 0.655000 ;
+      RECT 2.860000 1.495000 3.990000 1.665000 ;
+      RECT 2.860000 1.665000 3.145000 2.460000 ;
+      RECT 3.720000 1.665000 3.990000 2.460000 ;
+  END
+END sky130_fd_sc_hd__a2111o_1
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.netlist.tsv b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.netlist.tsv
new file mode 100644
index 0000000..0079b69
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.netlist.tsv
@@ -0,0 +1,14 @@
+sky130_fd_sc_hd__a2111o_1	A1:I A2:I B1:I C1:I D1:I VGND:I VNB:I VPB:I VPWR:I X:O

+Name	Formula	nd	ng	ns	nb	mname	m	w	l	mult	sa	sb	sd	topography	area	perim

+MMPA0	MOSFET	pndA	A1	VPWR	VPB	phighvt	1	1.0	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMPA1	MOSFET	pndA	A2	VPWR	VPB	phighvt	1	1.0	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMPB0	MOSFET	pndB	B1	pndA	VPB	phighvt	1	1.0	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMPC0	MOSFET	pndC	C1	pndB	VPB	phighvt	1	1.0	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMPD0	MOSFET	y	D1	pndC	VPB	phighvt	1	1.0	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMIPX	MOSFET	X	y	VPWR	VPB	phighvt	1	1.0	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMNA0	MOSFET	y	A1	sndA1	VNB	nshort	1	0.65	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMNA1	MOSFET	sndA1	A2	VGND	VNB	nshort	1	0.65	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMNB0	MOSFET	y	B1	VGND	VNB	nshort	1	0.65	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMNC0	MOSFET	y	C1	VGND	VNB	nshort	1	0.65	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMND0	MOSFET	y	D1	VGND	VNB	nshort	1	0.65	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

+MMINX	MOSFET	X	y	VGND	VNB	nshort	1	0.65	0.15	1	0.265	0.265	0.28	normal	0.063	1.14

diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.spice
new file mode 100644
index 0000000..8a18ce5
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.spice
@@ -0,0 +1,29 @@
+* NGSPICE file created from sky130_fd_sc_hd__a2111o_1.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hd__a2111o_1 A1 A2 B1 C1 D1 VGND VNB VPB VPWR X
+M1000 VPWR a_85_193# X VPB phighvt w=1e+06u l=150000u
++  ad=5.35e+11p pd=5.07e+06u as=2.9e+11p ps=2.58e+06u
+M1001 VGND a_85_193# X VNB nshort w=650000u l=150000u
++  ad=9.7175e+11p pd=6.89e+06u as=2.145e+11p ps=1.96e+06u
+M1002 a_414_297# C1 a_334_297# VPB phighvt w=1e+06u l=150000u
++  ad=3.6e+11p pd=2.72e+06u as=2.5e+11p ps=2.5e+06u
+M1003 a_516_297# B1 a_414_297# VPB phighvt w=1e+06u l=150000u
++  ad=8.5e+11p pd=5.7e+06u as=0p ps=0u
+M1004 VGND C1 a_85_193# VNB nshort w=650000u l=150000u
++  ad=0p pd=0u as=5.72e+11p ps=4.36e+06u
+M1005 a_516_297# A2 VPWR VPB phighvt w=1e+06u l=150000u
++  ad=0p pd=0u as=0p ps=0u
+M1006 a_334_297# D1 a_85_193# VPB phighvt w=1e+06u l=150000u
++  ad=0p pd=0u as=3.85e+11p ps=2.77e+06u
+M1007 a_660_47# A1 a_85_193# VNB nshort w=650000u l=150000u
++  ad=1.6575e+11p pd=1.81e+06u as=0p ps=0u
+M1008 VGND A2 a_660_47# VNB nshort w=650000u l=150000u
++  ad=0p pd=0u as=0p ps=0u
+M1009 a_85_193# B1 VGND VNB nshort w=650000u l=150000u
++  ad=0p pd=0u as=0p ps=0u
+M1010 VPWR A1 a_516_297# VPB phighvt w=1e+06u l=150000u
++  ad=0p pd=0u as=0p ps=0u
+M1011 a_85_193# D1 VGND VNB nshort w=650000u l=150000u
++  ad=0p pd=0u as=0p ps=0u
+.ends
+
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.svg b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.svg
new file mode 100644
index 0000000..f55242a
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.svg
@@ -0,0 +1,222 @@
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diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1.v b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.v
new file mode 100644
index 0000000..91d4359
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1.v
@@ -0,0 +1,131 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HD__A2111O_1_V
+`define SKY130_FD_SC_HD__A2111O_1_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include "sky130_fd_sc_hd__a2111o.v"
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hd__a2111o cell (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hd__a2111o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__a2111o cell (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HD__A2111O_1_V
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_100C_1v65.lib.json b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_100C_1v65.lib.json
new file mode 100644
index 0000000..e1d67d8
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_100C_1v65.lib.json
@@ -0,0 +1,3016 @@
+{
+  "area": 11.2608,
+  "cell_footprint": "a2111o",
+  "cell_leakage_power": 2.280553,
+  "driver_waveform_fall": "ramp",
+  "driver_waveform_rise": "ramp",
+  "leakage_power": [
+    {
+      "value": 2.977862,
+      "when": "!A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 10.8321219,
+      "when": "!A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.8903554,
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+    },
+    {
+      "value": 1.7395905,
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+    },
+    {
+      "value": 0.880639,
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+    },
+    {
+      "value": 1.5787329,
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+    },
+    {
+      "value": 0.8410537,
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+    },
+    {
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+    },
+    {
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+    },
+    {
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+    },
+    {
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+    },
+    {
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+    },
+    {
+      "value": 0.8806388,
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+    },
+    {
+      "value": 1.5787203,
+      "when": "!A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.8410537,
+      "when": "!A1&A2&B1&C1&D1"
+    },
+    {
+      "value": 0.8746138,
+      "when": "!A1&A2&B1&C1&!D1"
+    },
+    {
+      "value": 2.9777263,
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+    },
+    {
+      "value": 11.3759544,
+      "when": "A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.8903552,
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+    },
+    {
+      "value": 1.7395649,
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+    },
+    {
+      "value": 0.8806388,
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+    },
+    {
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+    },
+    {
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+    },
+    {
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+    },
+    {
+      "value": 1.061415,
+      "when": "A1&A2&!B1&!C1&D1"
+    },
+    {
+      "value": 3.1432905,
+      "when": "A1&A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.8671986,
+      "when": "A1&A2&!B1&C1&D1"
+    },
+    {
+      "value": 1.0267356,
+      "when": "A1&A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.8619165,
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+    },
+    {
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+    {
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+    },
+    {
+      "value": 0.8581102,
+      "when": "A1&A2&B1&C1&!D1"
+    }
+  ],
+  "pg_pin VGND": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VGND"
+  },
+  "pg_pin VNB": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VNB"
+  },
+  "pg_pin VPB": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPB"
+  },
+  "pg_pin VPWR": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPWR"
+  },
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+    "clock": "false",
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+    "related_power_pin": "VPWR",
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+  "pin X": {
+    "direction": "output",
+    "function": "(A1&A2) | (B1) | (C1) | (D1)",
+    "internal_power": [
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+        "cell_rise del_1_7_7": {
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+        },
+        "fall_transition del_1_7_7": {
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+            ]
+          ]
+        },
+        "related_pin": "D1",
+        "rise_transition del_1_7_7": {
+          "index_1": [
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+              0.0853629,
+              0.2096315,
+              0.5546544,
+              1.4989416
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+            [
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+              0.053453,
+              0.0913839,
+              0.2115433,
+              0.5536855,
+              1.4900443
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+            [
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+              0.1105807,
+              0.2191584,
+              0.5589839,
+              1.4902872
+            ]
+          ]
+        },
+        "timing_sense": "positive_unate",
+        "timing_type": "combinational"
+      }
+    ]
+  }
+}
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_100C_1v95.lib.json b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_100C_1v95.lib.json
new file mode 100644
index 0000000..eca3a85
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_100C_1v95.lib.json
@@ -0,0 +1,3016 @@
+{
+  "area": 11.2608,
+  "cell_footprint": "a2111o",
+  "cell_leakage_power": 3.78173,
+  "driver_waveform_fall": "ramp",
+  "driver_waveform_rise": "ramp",
+  "leakage_power": [
+    {
+      "value": 1.53749,
+      "when": "A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 1.3012739,
+      "when": "A1&A2&B1&C1&D1"
+    },
+    {
+      "value": 1.3261842,
+      "when": "A1&A2&B1&C1&!D1"
+    },
+    {
+      "value": 5.2498694,
+      "when": "!A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 18.2371487,
+      "when": "!A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 1.3701387,
+      "when": "!A1&!A2&!B1&C1&D1"
+    },
+    {
+      "value": 2.9324074,
+      "when": "!A1&!A2&!B1&C1&!D1"
+    },
+    {
+      "value": 1.3580679,
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+    },
+    {
+      "value": 2.6459501,
+      "when": "!A1&!A2&B1&!C1&!D1"
+    },
+    {
+      "value": 1.3082045,
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+    },
+    {
+      "value": 1.347195,
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+    },
+    {
+      "value": 5.2496545,
+      "when": "!A1&A2&!B1&!C1&D1"
+    },
+    {
+      "value": 19.6942196,
+      "when": "!A1&A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 1.3701384,
+      "when": "!A1&A2&!B1&C1&D1"
+    },
+    {
+      "value": 2.9323686,
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+    },
+    {
+      "value": 1.3580678,
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+    },
+    {
+      "value": 2.645923,
+      "when": "!A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 1.3082045,
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+    },
+    {
+      "value": 1.3471949,
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+    },
+    {
+      "value": 5.2495426,
+      "when": "A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 19.1117557,
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+    },
+    {
+      "value": 1.3701383,
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+    },
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+      "value": 2.9323484,
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+    },
+    {
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+    },
+    {
+      "value": 2.645909,
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+    },
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+    },
+    {
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+    },
+    {
+      "value": 1.5857351,
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+    {
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+    {
+      "value": 1.3407156,
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+    },
+    {
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+    },
+    {
+      "value": 1.3342782,
+      "when": "A1&A2&B1&!C1&D1"
+    }
+  ],
+  "pg_pin VGND": {
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+    "voltage_name": "VGND"
+  },
+  "pg_pin VNB": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VNB"
+  },
+  "pg_pin VPB": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPB"
+  },
+  "pg_pin VPWR": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPWR"
+  },
+  "pin A1": {
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+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002463,
+    "internal_power": {
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+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
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+          0.0055866,
+          0.0055951,
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+      },
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+          0.122474,
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+        ]
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+    },
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+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002603
+  },
+  "pin A2": {
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+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002306,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
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+          0.0531329,
+          0.122474,
+          0.282311,
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+      "rise_power power_inputs_1": {
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+          0.122474,
+          0.282311,
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+          1.5
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+    "related_power_pin": "VPWR",
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+  },
+  "pin B1": {
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+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002421,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.005256,
+          0.0052459,
+          0.0052443,
+          0.0052427,
+          0.0052412,
+          0.0052398
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          -0.0044373,
+          -0.004459,
+          -0.0045047,
+          -0.0046053,
+          -0.0048327
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002662
+  },
+  "pin C1": {
+    "capacitance": 0.002484,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002332,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.0046666,
+          0.0046574,
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+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
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+          -0.0042773,
+          -0.004294,
+          -0.0043279,
+          -0.0044019,
+          -0.0045681
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002636
+  },
+  "pin D1": {
+    "capacitance": 0.002461,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002263,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.0029258,
+          0.0029331,
+          0.0029518,
+          0.0029969,
+          0.0031029
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          -0.0018752,
+          -0.0018775,
+          -0.0018793,
+          -0.0018802,
+          -0.0018785
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.00266
+  },
+  "pin X": {
+    "direction": "output",
+    "function": "(A1&A2) | (B1) | (C1) | (D1)",
+    "internal_power": [
+      {
+        "fall_power power_outputs_1": {
+          "index_1": [
+            0.01,
+            0.02305058,
+            0.05313293,
+            0.1224745,
+            0.2823108,
+            0.6507428,
+            1.5
+          ],
+          "index_2": [
+            0.0005,
+            0.001407725,
+            0.003963381,
+            0.0111587,
+            0.03141678,
+            0.08845239,
+            0.2490334
+          ],
+          "values": [
+            [
+              0.0234902,
+              0.0214368,
+              0.0164152,
+              0.0043595,
+              -0.0326791,
+              -0.1409984,
+              -0.4464292
+            ],
+            [
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+              0.0161127,
+              0.0040444,
+              -0.0330102,
+              -0.1413286,
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+            ],
+            [
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+              0.015746,
+              0.0036939,
+              -0.033353,
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+            ],
+            [
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+            [
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+              0.0033396,
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+            ],
+            [
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+            ],
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+              0.0257848,
+              -0.0145229,
+              -0.123775,
+              -0.4296048
+            ]
+          ]
+        },
+        "related_pin": "A1",
+        "rise_power power_outputs_1": {
+          "index_1": [
+            0.01,
+            0.02305058,
+            0.05313293,
+            0.1224745,
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+        "timing_sense": "positive_unate",
+        "timing_type": "combinational"
+      }
+    ]
+  }
+}
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v56.lib.json b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v56.lib.json
new file mode 100644
index 0000000..4fa5e5c
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v56.lib.json
@@ -0,0 +1,3016 @@
+{
+  "area": 11.2608,
+  "cell_footprint": "a2111o",
+  "cell_leakage_power": 0.0002433553,
+  "driver_waveform_fall": "ramp",
+  "driver_waveform_rise": "ramp",
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+    },
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+    },
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+    },
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+    },
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+      "value": 3.624146e-05,
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+    "voltage_name": "VNB"
+  },
+  "pg_pin VPB": {
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+    "voltage_name": "VPB"
+  },
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+    "voltage_name": "VPWR"
+  },
+  "pin A1": {
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+    "clock": "false",
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+              0.0442108,
+              0.0960909,
+              0.2304885,
+              0.5823266,
+              1.4959637
+            ],
+            [
+              0.0174393,
+              0.0247205,
+              0.0442222,
+              0.0959517,
+              0.2308383,
+              0.5802318,
+              1.4970827
+            ],
+            [
+              0.0175562,
+              0.0248177,
+              0.0441608,
+              0.095312,
+              0.2296409,
+              0.5837165,
+              1.5071056
+            ],
+            [
+              0.0189012,
+              0.0257643,
+              0.0445731,
+              0.0957278,
+              0.2312976,
+              0.5818928,
+              1.4983776
+            ],
+            [
+              0.0227166,
+              0.0290282,
+              0.0460713,
+              0.0961375,
+              0.2294644,
+              0.5830847,
+              1.5031821
+            ],
+            [
+              0.0309479,
+              0.0368061,
+              0.0524333,
+              0.0976112,
+              0.2314674,
+              0.5767085,
+              1.4913355
+            ],
+            [
+              0.0468357,
+              0.0540577,
+              0.0687594,
+              0.1083561,
+              0.2322735,
+              0.5854096,
+              1.4871355
+            ]
+          ]
+        },
+        "timing_sense": "positive_unate",
+        "timing_type": "combinational"
+      }
+    ]
+  }
+}
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v65.lib.json b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v65.lib.json
new file mode 100644
index 0000000..ce87b31
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v65.lib.json
@@ -0,0 +1,3016 @@
+{
+  "area": 11.2608,
+  "cell_footprint": "a2111o",
+  "cell_leakage_power": 0.0004970863,
+  "driver_waveform_fall": "ramp",
+  "driver_waveform_rise": "ramp",
+  "leakage_power": [
+    {
+      "value": 5.1905346e-05,
+      "when": "A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "A1&A2&B1&C1&D1"
+    },
+    {
+      "value": 6.078963e-05,
+      "when": "A1&A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0007846,
+      "when": "!A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.000859,
+      "when": "!A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "!A1&!A2&!B1&C1&D1"
+    },
+    {
+      "value": 6.0923001e-05,
+      "when": "!A1&!A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0007834,
+      "when": "!A1&!A2&B1&!C1&D1"
+    },
+    {
+      "value": 5.2194777e-05,
+      "when": "!A1&!A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "!A1&!A2&B1&C1&D1"
+    },
+    {
+      "value": 6.0791751e-05,
+      "when": "!A1&!A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0007846,
+      "when": "!A1&A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.0008754,
+      "when": "!A1&A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "!A1&A2&!B1&C1&D1"
+    },
+    {
+      "value": 6.0923001e-05,
+      "when": "!A1&A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0007834,
+      "when": "!A1&A2&B1&!C1&D1"
+    },
+    {
+      "value": 5.2194777e-05,
+      "when": "!A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "!A1&A2&B1&C1&D1"
+    },
+    {
+      "value": 6.0791751e-05,
+      "when": "!A1&A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0007846,
+      "when": "A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.0008711,
+      "when": "A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "A1&!A2&!B1&C1&D1"
+    },
+    {
+      "value": 6.0923001e-05,
+      "when": "A1&!A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0007834,
+      "when": "A1&!A2&B1&!C1&D1"
+    },
+    {
+      "value": 5.2194777e-05,
+      "when": "A1&!A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "A1&!A2&B1&C1&D1"
+    },
+    {
+      "value": 6.0791751e-05,
+      "when": "A1&!A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0007838,
+      "when": "A1&A2&!B1&!C1&D1"
+    },
+    {
+      "value": 6.9042028e-05,
+      "when": "A1&A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0007833,
+      "when": "A1&A2&!B1&C1&D1"
+    },
+    {
+      "value": 6.0663964e-05,
+      "when": "A1&A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0007834,
+      "when": "A1&A2&B1&!C1&D1"
+    }
+  ],
+  "pg_pin VGND": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VGND"
+  },
+  "pg_pin VNB": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VNB"
+  },
+  "pg_pin VPB": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPB"
+  },
+  "pg_pin VPWR": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPWR"
+  },
+  "pin A1": {
+    "capacitance": 0.0023,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002194,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
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+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.0036075,
+          0.0036005,
+          0.0036012,
+          0.0036027,
+          0.0036061,
+          0.003614
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
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+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          -0.0029037,
+          -0.002892,
+          -0.0028651,
+          -0.0028031
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002405
+  },
+  "pin A2": {
+    "capacitance": 0.002167,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002066,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
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+          0.0531329,
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+          1.5
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+          0.0030001,
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+        ]
+      },
+      "rise_power power_inputs_1": {
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+          0.0531329,
+          0.122474,
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+          0.650743,
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+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002269
+  },
+  "pin B1": {
+    "capacitance": 0.002322,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002189,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.0031284,
+          0.0031294,
+          0.0031315,
+          0.0031364
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
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+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          -0.0028902,
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+      }
+    },
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+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002455
+  },
+  "pin C1": {
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+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002134,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
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+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
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+          1.5
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+      },
+      "rise_power power_inputs_1": {
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+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
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+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002429
+  },
+  "pin D1": {
+    "capacitance": 0.002272,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002073,
+    "internal_power": {
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+        "index_1": [
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+          0.122474,
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+          0.0020525,
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+      },
+      "rise_power power_inputs_1": {
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+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
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+        "values": [
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+          -0.0014302,
+          -0.0014319,
+          -0.0014359,
+          -0.001445,
+          -0.0014661
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.00247
+  },
+  "pin X": {
+    "direction": "output",
+    "function": "(A1&A2) | (B1) | (C1) | (D1)",
+    "internal_power": [
+      {
+        "fall_power power_outputs_1": {
+          "index_1": [
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+            0.02305058,
+            0.05313293,
+            0.1224745,
+            0.2823108,
+            0.6507428,
+            1.5
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+            0.003541162,
+            0.009423965,
+            0.02507965,
+            0.06674357,
+            0.1776222
+          ],
+          "values": [
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+            ]
+          ]
+        },
+        "related_pin": "A1",
+        "rise_power power_outputs_1": {
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+            0.1224745,
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+            0.003541162,
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+            0.02507965,
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+          ],
+          "values": [
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+              0.046283,
+              0.1027195,
+              0.2510388
+            ]
+          ]
+        }
+      },
+      {
+        "fall_power power_outputs_1": {
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+            0.02507965,
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+          "values": [
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+            ]
+          ]
+        },
+        "related_pin": "A2",
+        "rise_power power_outputs_1": {
+          "index_1": [
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+            0.05313293,
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+          ],
+          "values": [
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+        "timing_type": "combinational"
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+      {
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+        "fall_transition del_1_7_7": {
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+        "rise_transition del_1_7_7": {
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+              0.5713672,
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+            ],
+            [
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+              0.0499252,
+              0.0923247,
+              0.2227297,
+              0.5675783,
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+            [
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+              0.2231187,
+              0.5748276,
+              1.4923781
+            ]
+          ]
+        },
+        "timing_sense": "positive_unate",
+        "timing_type": "combinational"
+      }
+    ]
+  }
+}
\ No newline at end of file
diff --git a/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v76.lib.json b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v76.lib.json
new file mode 100644
index 0000000..4d87108
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_hd__a2111o_1__ff_n40C_1v76.lib.json
@@ -0,0 +1,3016 @@
+{
+  "area": 11.2608,
+  "cell_footprint": "a2111o",
+  "cell_leakage_power": 0.001119943,
+  "driver_waveform_fall": "ramp",
+  "driver_waveform_rise": "ramp",
+  "leakage_power": [
+    {
+      "value": 9.7617667e-05,
+      "when": "A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "A1&A2&B1&C1&D1"
+    },
+    {
+      "value": 0.0001254,
+      "when": "A1&A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0017897,
+      "when": "!A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.0018867,
+      "when": "!A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "!A1&!A2&!B1&C1&D1"
+    },
+    {
+      "value": 0.0001256,
+      "when": "!A1&!A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0017878,
+      "when": "!A1&!A2&B1&!C1&D1"
+    },
+    {
+      "value": 9.8052175e-05,
+      "when": "!A1&!A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "!A1&!A2&B1&C1&D1"
+    },
+    {
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+      "when": "!A1&!A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0017897,
+      "when": "!A1&A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.0019075,
+      "when": "!A1&A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "!A1&A2&!B1&C1&D1"
+    },
+    {
+      "value": 0.0001256,
+      "when": "!A1&A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0017878,
+      "when": "!A1&A2&B1&!C1&D1"
+    },
+    {
+      "value": 9.8052175e-05,
+      "when": "!A1&A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "!A1&A2&B1&C1&D1"
+    },
+    {
+      "value": 0.0001254,
+      "when": "!A1&A2&B1&C1&!D1"
+    },
+    {
+      "value": 0.0017897,
+      "when": "A1&!A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.0019015,
+      "when": "A1&!A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "A1&!A2&!B1&C1&D1"
+    },
+    {
+      "value": 0.0001256,
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+    },
+    {
+      "value": 0.0017878,
+      "when": "A1&!A2&B1&!C1&D1"
+    },
+    {
+      "value": 9.8052175e-05,
+      "when": "A1&!A2&B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
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+    },
+    {
+      "value": 0.0001254,
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+    },
+    {
+      "value": 0.0017887,
+      "when": "A1&A2&!B1&!C1&D1"
+    },
+    {
+      "value": 0.0001362,
+      "when": "A1&A2&!B1&!C1&!D1"
+    },
+    {
+      "value": 0.0017877,
+      "when": "A1&A2&!B1&C1&D1"
+    },
+    {
+      "value": 0.000125,
+      "when": "A1&A2&!B1&C1&!D1"
+    },
+    {
+      "value": 0.0017878,
+      "when": "A1&A2&B1&!C1&D1"
+    }
+  ],
+  "pg_pin VGND": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VGND"
+  },
+  "pg_pin VNB": {
+    "pg_type": "primary_ground",
+    "voltage_name": "VNB"
+  },
+  "pg_pin VPB": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPB"
+  },
+  "pg_pin VPWR": {
+    "pg_type": "primary_power",
+    "voltage_name": "VPWR"
+  },
+  "pin A1": {
+    "capacitance": 0.002355,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002252,
+    "internal_power": {
+      "fall_power power_inputs_1": {
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+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
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+          0.0041762,
+          0.0041801,
+          0.0041888,
+          0.0042091
+        ]
+      },
+      "rise_power power_inputs_1": {
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+          0.0531329,
+          0.122474,
+          0.282311,
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+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002458
+  },
+  "pin A2": {
+    "capacitance": 0.002215,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002115,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
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+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
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+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
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+          -0.0035001,
+          -0.003501,
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+          -0.0035071
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002314
+  },
+  "pin B1": {
+    "capacitance": 0.002372,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002237,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
+          0.0036412,
+          0.003639,
+          0.003634,
+          0.0036343,
+          0.0036351,
+          0.003637,
+          0.0036413
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
+          -0.0031392,
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+          -0.0032608,
+          -0.0032727,
+          -0.0032999,
+          -0.0033627,
+          -0.0035074
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002506
+  },
+  "pin C1": {
+    "capacitance": 0.002328,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002175,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.0033931,
+          0.0033907,
+          0.0033852,
+          0.0033725,
+          0.0033433
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          -0.003266,
+          -0.0032696,
+          -0.0032779,
+          -0.003297,
+          -0.0033411
+        ]
+      }
+    },
+    "max_transition": 1.5,
+    "related_ground_pin": "VGND",
+    "related_power_pin": "VPWR",
+    "rise_capacitance": 0.002481
+  },
+  "pin D1": {
+    "capacitance": 0.002324,
+    "clock": "false",
+    "direction": "input",
+    "fall_capacitance": 0.002121,
+    "internal_power": {
+      "fall_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          0.0023307,
+          0.0023364,
+          0.0023495,
+          0.0023796,
+          0.0024489
+        ]
+      },
+      "rise_power power_inputs_1": {
+        "index_1": [
+          0.01,
+          0.0230506,
+          0.0531329,
+          0.122474,
+          0.282311,
+          0.650743,
+          1.5
+        ],
+        "values": [
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+          -0.0016014,
+          -0.0016073,
+          -0.0016092,
+          -0.0016134,
+          -0.0016232,
+          -0.0016457
+        ]
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