blob: fc6c472c61bcde25f7c3167f364b5611d2266bbf [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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},
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}
},
"pin,M0": {
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"internal_node": "M0",
"related_ground_pin": "VNB",
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},
"pin,SCE": {
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},
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{
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0.01,
0.5,
1.5
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"timing_type": "setup_rising",
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},
{
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0.01,
0.5,
1.5
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"index_2": [
0.01,
0.5,
1.5
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},
"related_pin": "CLK",
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0.5,
1.5
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0.01,
0.5,
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},
"sim_opt": "runlvl=5 accurate=1",
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}
]
},
"statetable,CLK GATE SCE,M0": {
"table": [
"L L L : - : L",
"L L H : - : H",
"L H L : - : H",
"L H H : - : H",
"H - - : - : N"
]
}
}