blob: 2e5451786ff6b72acfaabb19a132004ca9b63fc5 [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge",
"driver_waveform_fall": "ramp",
"driver_waveform_rise": "ramp",
"leakage_power": [
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"when": "CLK&!GATE&!GCLK"
},
{
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},
{
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{
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{
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{
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"voltage_name": "VGND"
},
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"physical_connection": "device_layer",
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},
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"related_pin": "CLK",
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{
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}
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},
"timing_sense": "positive_unate",
"timing_type": "combinational"
}
},
"pin,M0": {
"direction": "internal",
"internal_node": "M0",
"related_ground_pin": "VNB",
"related_power_pin": "VPWR"
},
"statetable,CLK GATE,M0": {
"table": [
"L L : - : L",
"L H : - : H",
"H - : - : N"
]
}
}