{
  "area": 26.2752,
  "cell_footprint": "sky130_fd_sc_hd__dfxbp",
  "cell_leakage_power": 0.0006917658,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff,IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
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      "value": 0.0007082,
      "when": "CLK&D&!Q&Q_N"
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    {
      "value": 0.0006451,
      "when": "!CLK&!D&!Q&Q_N"
    },
    {
      "value": 0.0007361,
      "when": "CLK&!D&Q&!Q_N"
    },
    {
      "value": 0.0006735,
      "when": "!CLK&D&Q&!Q_N"
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    {
      "value": 0.000711,
      "when": "!CLK&D&!Q&Q_N"
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    {
      "value": 0.0006844,
      "when": "CLK&!D&!Q&Q_N"
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    {
      "value": 0.00065,
      "when": "CLK&D&Q&!Q_N"
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    {
      "value": 0.0007258,
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  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
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    "clock": "true",
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          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
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      "rise_power,power_inputs_1": {
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        "values": [
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          0.0099592,
          0.0105663
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    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001483,
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        "values": [
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      "related_output_pin": "Q",
      "related_pin": "CLK",
      "rise_constraint,constraint_3_0_1": {
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          5.0
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        "values": [
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      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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      "rise_power,power_inputs_1": {
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    "max_transition": 5.0,
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        "related_pin": "CLK",
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            5.0
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          "index_2": [
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            5.0
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        "sim_opt": "runlvl=5 accurate=1",
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    "function": "IQ",
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    "max_capacitance": 0.311289,
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    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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      "rise_transition,del_1_7_7": {
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      "timing_sense": "non_unate",
      "timing_type": "rising_edge"
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  },
  "pin,Q_N": {
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    "function": "IQ_N",
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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