)]}'
{
  "commit": "efaf575772a8ea1b66ef7dbc1bea51617367ec06",
  "tree": "f4ef32b4b873c5d8fad80f02eb6ee86e349a23ca",
  "parents": [
    "549fe825c3514f67c7210d6add6eef00b6641ccf",
    "47eb2ceb6756b27bba3b55c7f4a9d3d5a470f8a6"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:04:17 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:04:17 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}