blob: b706dc5f40e71e1b6b5610ce64fc449eaa89f30b [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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}
},
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},
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5.0
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},
{
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2.5,
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2.5,
5.0
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5.0
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},
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}
]
},
"statetable,CLK GATE SCE,M0": {
"table": [
"L L L : - : L",
"L L H : - : H",
"L H L : - : H",
"L H H : - : H",
"H - - : - : N"
]
}
}