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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_hd / cda3df2a40a56fbc51a320205445be338492363e / . / cells / sdlclkp / sky130_fd_sc_hd__sdlclkp_1__ss_n40C_1v60_ccsnoise.lib.json
blob: 18cbd19e513e9efcccddfeecb106bfe4eb45b03e [file] [log] [blame]
{
"area": 18.768,
"cell_footprint": "sky130_fd_sc_hd__sdlclkp",
"cell_leakage_power": 0.002137153,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"driver_waveform_fall": "ramp",
"driver_waveform_rise": "ramp",
"leakage_power": [
{
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"when": "CLK&!GATE&!GCLK&!SCE"
},
{
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},
{
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{
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{
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{
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{
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],
"pg_pin,VGND": {
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"related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
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},
"pg_pin,VPB": {
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},
"pg_pin,VPWR": {
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"voltage_name": "VPWR"
},
"pin,CLK": {
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"ccsn_first_stage": {
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"statetable,CLK GATE SCE,M0": {
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}
}