{
  "area": 18.768,
  "cell_footprint": "sky130_fd_sc_hd__sdlclkp",
  "cell_leakage_power": 15.10817,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
    {
      "value": 16.6619909,
      "when": "CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 12.4001103,
      "when": "!CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 12.4014186,
      "when": "!CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 14.21642,
      "when": "CLK&!GATE&GCLK&SCE"
    },
    {
      "value": 10.5124167,
      "when": "!CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 15.6412483,
      "when": "!CLK&!GATE&!GCLK&!SCE"
    },
    {
      "value": 14.2151144,
      "when": "CLK&GATE&GCLK&!SCE"
    },
    {
      "value": 12.327444,
      "when": "CLK&GATE&GCLK&SCE"
    },
    {
      "value": 19.7092422,
      "when": "CLK&GATE&!GCLK&!SCE"
    },
    {
      "value": 19.710539,
      "when": "CLK&!GATE&!GCLK&SCE"
    },
    {
      "value": 17.8216801,
      "when": "CLK&GATE&!GCLK&SCE"
    },
    {
      "value": 15.6804063,
      "when": "CLK&!GATE&GCLK&!SCE"
    }
  ],
  "pg_pin,VGND": {
    "pg_type": "primary_ground",
    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
  },
  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
    "voltage_name": "VNB"
  },
  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
    "voltage_name": "VPB"
  },
  "pg_pin,VPWR": {
    "pg_type": "primary_power",
    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
  },
  "pin,CLK": {
    "capacitance": 0.003504,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.003308,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
          5.0
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        "values": [
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          0.0144923,
          0.0147254,
          0.0146746,
          0.0146552,
          0.0147242,
          0.0150422
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      },
      "rise_power,power_inputs_1": {
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          0.01,
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          0.0793701,
          0.223607,
          0.629961,
          1.77477,
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        "values": [
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          0.0067965,
          0.0067576,
          0.0067426,
          0.006795
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.0037,
    "timing": {
      "fall_constraint,constraint_3_0_1": {
        "index_1": [
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          5.0
        ],
        "values": [
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          8.3333333
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      },
      "related_output_pin": "GCLK",
      "related_pin": "CLK",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin,GATE": {
    "capacitance": 0.001754,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.001688,
    "internal_power": {
      "fall_power,power_inputs_1": {
        "index_1": [
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          0.0793701,
          0.223607,
          0.629961,
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        "values": [
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          0.0195591
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      },
      "rise_power,power_inputs_1": {
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        "values": [
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          0.0116484,
          0.0115893,
          0.0115397,
          0.0115165
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001819,
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      {
        "fall_constraint,vio_3_3_1": {
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            0.01,
            2.5,
            5.0
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          "index_2": [
            0.01,
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            5.0
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          "values": [
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              0.4103252,
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              1.8861471
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            [
              -0.1642109,
              0.7142803,
              1.2859763
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            [
              -0.4429381,
              0.4245667,
              0.9926006
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
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            5.0
          ],
          "index_2": [
            0.01,
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            5.0
          ],
          "values": [
            [
              0.2070781,
              0.8640117,
              1.2086569
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              -0.1294209,
              0.4945537,
              0.8172262
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            [
              -0.1884216,
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              0.7490703
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint,vio_3_3_1": {
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            5.0
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          "index_2": [
            0.01,
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            5.0
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          "values": [
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              -0.399001,
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              -1.8382019
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              0.170042,
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              -1.2801452
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            [
              0.4469381,
              -0.4187357,
              -0.9867695
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
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              -0.1078633,
              -0.7281758,
              -1.0307067
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            [
              0.2304668,
              -0.366042,
              -0.6594176
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            [
              0.3920065,
              -0.2026712,
              -0.4978779
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin,GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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          0.2236068,
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          1.774768,
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          0.3357033
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            0.0034495,
            -0.0071712,
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            0.002671,
            -0.0079238,
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            0.0060829,
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            -0.0082272,
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            -0.136707,
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            -0.1365813,
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            -0.4198091
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      "related_pin": "CLK",
      "rise_power,power_outputs_1": {
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            0.4337594
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        ]
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    },
    "max_capacitance": 0.098887,
    "max_transition": 1.496232,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "state_function": "(CLK*M0)",
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      "cell_rise,del_1_7_7": {
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      "fall_transition,del_1_7_7": {
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        "index_2": [
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      "related_pin": "CLK",
      "rise_transition,del_1_7_7": {
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        "index_2": [
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        "values": [
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        ]
      },
      "timing_sense": "positive_unate",
      "timing_type": "combinational"
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  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VNB",
    "related_power_pin": "VPWR"
  },
  "pin,SCE": {
    "capacitance": 0.001746,
    "clock": "false",
    "clock_gate_test_pin": "true",
    "direction": "input",
    "fall_capacitance": 0.00168,
    "internal_power": {
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        "index_1": [
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        "values": [
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      "rise_power,power_inputs_1": {
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          0.629961,
          1.77477,
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        ],
        "values": [
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001812,
    "timing": [
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
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              0.4304668,
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              -0.1568867,
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              1.1468161
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            [
              -0.4411071,
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              0.8534404
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
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            0.01,
            2.5,
            5.0
          ],
          "index_2": [
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            5.0
          ],
          "values": [
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              1.3551413
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              -0.0927998,
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            [
              -0.1554626,
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              0.9010478
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -0.4173115,
              -1.2134052,
              -1.7008727
            ],
            [
              0.1608867,
              -0.6370381,
              -1.1391539
            ],
            [
              0.4451071,
              -0.3473245,
              -0.8494404
            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint,vio_3_3_1": {
          "index_1": [
            0.01,
            2.5,
            5.0
          ],
          "index_2": [
            0.01,
            2.5,
            5.0
          ],
          "values": [
            [
              -0.1280049,
              -0.8178975,
              -1.1845153
            ],
            [
              0.1920146,
              -0.4612568,
              -0.8168883
            ],
            [
              0.342568,
              -0.3033792,
              -0.6553486
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}