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| "area": 25.024, | |
| "cell_footprint": "sky130_fd_sc_hd__mux4", | |
| "cell_leakage_power": 0.002803437, | |
| "driver_waveform_fall": "ramp", | |
| "driver_waveform_rise": "ramp", | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
| "value": 0.0043639, | |
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| { | |
| "value": 0.0004522, | |
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| { | |
| "value": 0.0021452, | |
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| { | |
| "value": 0.0012256, | |
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| { | |
| "value": 0.0012218, | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
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| { | |
| "value": 0.0012244, | |
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| } | |
| ], | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,A0": { | |
| "capacitance": 0.001749, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001659, | |
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| 0.0230506, | |
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| 0.282311, | |
| 0.650743, | |
| 1.5 | |
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| 0.0074698 | |
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| ] | |
| } | |
| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.00184 | |
| }, | |
| "pin,A1": { | |
| "capacitance": 0.001741, | |
| "clock": "false", | |
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| "fall_capacitance": 0.001647, | |
| "internal_power": { | |
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| 0.0026315 | |
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| }, | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.001835 | |
| }, | |
| "pin,A2": { | |
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| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001628, | |
| "internal_power": { | |
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| "rise_power,power_inputs_1": { | |
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| 0.0039021, | |
| 0.0039204 | |
| ] | |
| } | |
| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.00177 | |
| }, | |
| "pin,A3": { | |
| "capacitance": 0.001703, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001625, | |
| "internal_power": { | |
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| 0.0230506, | |
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| ], | |
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| 0.0022818 | |
| ] | |
| }, | |
| "rise_power,power_inputs_1": { | |
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| 0.0531329, | |
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| 0.282311, | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.001782 | |
| }, | |
| "pin,S0": { | |
| "capacitance": 0.005685, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.005508, | |
| "internal_power": { | |
| "fall_power,power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0230506, | |
| 0.0531329, | |
| 0.122474, | |
| 0.282311, | |
| 0.650743, | |
| 1.5 | |
| ], | |
| "values": [ | |
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| 0.0153234, | |
| 0.0153612, | |
| 0.0154486, | |
| 0.0156499 | |
| ] | |
| }, | |
| "rise_power,power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0230506, | |
| 0.0531329, | |
| 0.122474, | |
| 0.282311, | |
| 0.650743, | |
| 1.5 | |
| ], | |
| "values": [ | |
| 0.0016191, | |
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| 0.0010059, | |
| 0.0009987, | |
| 0.0009822, | |
| 0.0009441, | |
| 0.0008564 | |
| ] | |
| } | |
| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.005863 | |
| }, | |
| "pin,S1": { | |
| "capacitance": 0.00315, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.003029, | |
| "internal_power": { | |
| "fall_power,power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0230506, | |
| 0.0531329, | |
| 0.122474, | |
| 0.282311, | |
| 0.650743, | |
| 1.5 | |
| ], | |
| "values": [ | |
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| 0.0082484, | |
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| 0.0080458, | |
| 0.0081077, | |
| 0.0082504, | |
| 0.0085793 | |
| ] | |
| }, | |
| "rise_power,power_inputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.0230506, | |
| 0.0531329, | |
| 0.122474, | |
| 0.282311, | |
| 0.650743, | |
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| ], | |
| "values": [ | |
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| ] | |
| } | |
| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.003271 | |
| }, | |
| "pin,X": { | |
| "direction": "output", | |
| "function": "(A0&!S0&!S1) | (A1&S0&!S1) | (A2&!S0&S1) | (A3&S0&S1)", | |
| "internal_power": [ | |
| { | |
| "fall_power,power_outputs_1": { | |
| "index_1": [ | |
| 0.01, | |
| 0.02305058, | |
| 0.05313293, | |
| 0.1224745, | |
| 0.2823108, | |
| 0.6507428, | |
| 1.5 | |
| ], | |
| "index_2": [ | |
| 0.0005, | |
| 0.001601635, | |
| 0.005130469, | |
| 0.01643428, | |
| 0.05264343, | |
| 0.1686311, | |
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| ], | |
| "values": [ | |
| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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