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| { | |
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| { | |
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| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
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| "pg_pin,VNB": { | |
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| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
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| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
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| "voltage_name": "VPB" | |
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| "voltage_name": "VPWR" | |
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| "pin,A3": { | |
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| }, | |
| "pin,S0": { | |
| "capacitance": 0.005083, | |
| "clock": "false", | |
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| "fall_capacitance": 0.004769, | |
| "internal_power": { | |
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| "rise_power,power_inputs_1": { | |
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| }, | |
| "max_transition": 1.5, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.005397 | |
| }, | |
| "pin,S1": { | |
| "capacitance": 0.002991, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.002876, | |
| "internal_power": { | |
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| "rise_power,power_inputs_1": { | |
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| }, | |
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| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.003107 | |
| }, | |
| "pin,X": { | |
| "direction": "output", | |
| "function": "(A0&!S0&!S1) | (A1&S0&!S1) | (A2&!S0&S1) | (A3&S0&S1)", | |
| "internal_power": [ | |
| { | |
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| 1.5 | |
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| "index_2": [ | |
| 0.0005, | |
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| [ | |
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| [ | |
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| [ | |
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