{
  "area": 26.2752,
  "cell_footprint": "sky130_fd_sc_hd__dfxbp",
  "cell_leakage_power": 14.0979,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff,IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
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      "value": 15.9526898,
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    {
      "value": 13.4416753,
      "when": "!CLK&!D&!Q&Q_N"
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    {
      "value": 13.7578411,
      "when": "CLK&!D&Q&!Q_N"
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    {
      "value": 13.396587,
      "when": "!CLK&D&Q&!Q_N"
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    {
      "value": 15.7042628,
      "when": "!CLK&D&!Q&Q_N"
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    {
      "value": 12.6761259,
      "when": "CLK&!D&!Q&Q_N"
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    {
      "value": 13.6607055,
      "when": "CLK&D&Q&!Q_N"
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    {
      "value": 14.1933008,
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  "pg_pin,VGND": {
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    "related_bias_pin": "VPB",
    "voltage_name": "VGND"
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  "pg_pin,VNB": {
    "pg_type": "nwell",
    "physical_connection": "device_layer",
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  "pg_pin,VPB": {
    "pg_type": "pwell",
    "physical_connection": "device_layer",
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  "pg_pin,VPWR": {
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    "related_bias_pin": "VNB",
    "voltage_name": "VPWR"
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      "rise_power,power_inputs_1": {
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    "max_transition": 10.0,
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    "related_power_pin": "VPWR",
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      "related_output_pin": "Q",
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      "rise_constraint,constraint_3_0_1": {
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      "sim_opt": "runlvl=5 accurate=1",
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      "rise_power,power_inputs_1": {
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    "max_transition": 10.0,
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        "related_pin": "CLK",
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10
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      {
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        "related_pin": "CLK",
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        "sim_opt": "runlvl=5 accurate=1",
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    "max_capacitance": 0.917063,
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    "related_power_pin": "VPWR",
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      "cell_rise,del_1_7_7": {
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      "timing_sense": "non_unate",
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    "function": "IQ_N",
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}