{
  "area": 11.2608,
  "cell_footprint": "or3b",
  "cell_leakage_power": 0.003331851,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
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      "value": 0.0053899,
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    },
    {
      "value": 0.0046117,
      "when": "!A&!B&!C_N"
    },
    {
      "value": 0.0032644,
      "when": "!A&B&C_N"
    },
    {
      "value": 0.0024951,
      "when": "!A&B&!C_N"
    },
    {
      "value": 0.0031463,
      "when": "A&!B&C_N"
    },
    {
      "value": 0.0024858,
      "when": "A&!B&!C_N"
    },
    {
      "value": 0.0027968,
      "when": "A&B&C_N"
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    {
      "value": 0.0024648,
      "when": "A&B&!C_N"
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  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002562
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  "pin B": {
    "capacitance": 0.002374,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.002224,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002524
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  "pin C_N": {
    "capacitance": 0.001492,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001426,
    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
        "index_1": [
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          0.0531329,
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          0.650743,
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        "values": [
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          0.0031416,
          0.0033382,
          0.0037914
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001557
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  "pin X": {
    "direction": "output",
    "function": "(A) | (B) | (!C_N)",
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      {
        "fall_power power_outputs_1": {
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        "related_pin": "B",
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      {
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    "max_capacitance": 0.469675,
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    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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        "cell_rise del_1_7_7": {
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        "rise_transition del_1_7_7": {
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