| { |
| "area": 40.0384, |
| "cell_footprint": "lsbuf_lh_isowell_tap", |
| "cell_leakage_power": 19.46273, |
| "comp_attribute input_voltage_range": [ |
| 1.2, |
| 2.1 |
| ], |
| "comp_attribute output_voltage_range": [ |
| 1.2, |
| 2.1 |
| ], |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "is_level_shifter": "true", |
| "leakage_power": [ |
| { |
| "value": 23.1816593, |
| "when": "A" |
| }, |
| { |
| "value": 15.743808, |
| "when": "!A" |
| } |
| ], |
| "level_shifter_type": "LH", |
| "pg_pin LOWLVPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "LOWLVPWR" |
| }, |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "backup_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "std_cell_main_rail": "true", |
| "voltage_name": "VPWR" |
| }, |
| "pin A": { |
| "capacitance": 0.006125, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.006091, |
| "input_signal_level": "lowlvpwr", |
| "level_shifter_data_pin": "true", |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "LOWLVPWR", |
| "rise_capacitance": 0.006159 |
| }, |
| "pin X": { |
| "direction": "output", |
| "function": "(A)", |
| "internal_power": { |
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| }, |
| "related_pin": "A", |
| "rise_power power_outputs_1": { |
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| }, |
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| "max_transition": 1.506753, |
| "power_down_function": "(!LOWLVPWR+!VPWR+VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": { |
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| ] |
| ] |
| }, |
| "cell_rise del_1_7_7": { |
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| 0.01, |
| 0.0230506, |
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| }, |
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| }, |
| "timing_sense": "positive_unate", |
| "timing_type": "combinational" |
| } |
| } |
| } |
