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  "area": 13.7632,
  "cell_footprint": "inputisolatch",
  "cell_leakage_power": 12.32722,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "is_isolation_cell": "true",
  "latch IQ,IQ_N": {
    "data_in": "D",
    "enable": "SLEEP_B"
  },
  "leakage_power": [
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      "value": 9.7966453,
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      "value": 14.5111638,
      "when": "!D&!SLEEP_B&!Q"
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    {
      "value": 14.5278154,
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    {
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    {
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    {
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    "voltage_name": "VNB"
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    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "clock": "false",
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      {
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    "function": "IQ",
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        "cell_rise del_1_7_7": {
          "index_1": [
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          "values": [
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        "fall_transition del_1_7_7": {
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          "values": [
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              0.0438485,
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        "related_pin": "SLEEP_B",
        "rise_transition del_1_7_7": {
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          "values": [
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        "timing_sense": "non_unate",
        "timing_type": "rising_edge"
      }
    ]
  },
  "pin SLEEP_B": {
    "capacitance": 0.001712,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.00166,
    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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          0.0085656,
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    },
    "isolation_cell_enable_pin": "true",
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001763,
    "timing": {
      "related_output_pin": "Q",
      "related_pin": "SLEEP_B",
      "rise_constraint constraint_3_0_1": {
        "index_1": [
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        ],
        "values": [
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      },
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  }
}