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| "cell_footprint": "dlxbn", |
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| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
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| "data_in": "D", |
| "enable": "!GATE_N" |
| }, |
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| { |
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| "when": "D&!GATE_N&Q&!Q_N" |
| }, |
| { |
| "value": 0.0003601, |
| "when": "!D&GATE_N&!Q&Q_N" |
| }, |
| { |
| "value": 0.0003617, |
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| { |
| "value": 0.0004524, |
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| }, |
| { |
| "value": 0.0004259, |
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| }, |
| { |
| "value": 0.0004327, |
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| } |
| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
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| "clock": "false", |
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| 0.0316228, |
| 0.1, |
| 0.316228, |
| 1.0, |
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| "rise_power power_inputs_1": { |
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| "max_transition": 10.0, |
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| "related_power_pin": "VPWR", |
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| "timing": [ |
| { |
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| 5.0, |
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| [ |
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| "related_pin": "GATE_N", |
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| [ |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 9.9999999 |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "GATE_N", |
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| } |
| ] |
| }, |
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| "clock": "true", |
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| "rise_power power_inputs_1": { |
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| }, |
| "max_transition": 10.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| "timing": { |
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| }, |
| "related_output_pin": "Q", |
| "related_pin": "GATE_N", |
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| "timing_type": "min_pulse_width", |
| "violation_delay_degrade_pct": 10 |
| } |
| }, |
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| "function": "IQ", |
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| { |
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| "related_pin": "D", |
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| ], |
| "max_capacitance": 0.311289, |
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| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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