{
  "area": 22.5216,
  "cell_footprint": "dlrbp",
  "cell_leakage_power": 19.11685,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "latch IQ,IQ_N": {
    "clear": "!RESET_B",
    "data_in": "D",
    "enable": "GATE"
  },
  "leakage_power": [
    {
      "value": 21.2810143,
      "when": "RESET_B&D&GATE&Q&!Q_N"
    },
    {
      "value": 17.468416,
      "when": "RESET_B&!D&!GATE&!Q&Q_N"
    },
    {
      "value": 16.3828879,
      "when": "!RESET_B&!D&GATE&!Q&Q_N"
    },
    {
      "value": 16.9551715,
      "when": "RESET_B&!D&GATE&!Q&Q_N"
    },
    {
      "value": 21.1644071,
      "when": "RESET_B&D&!GATE&Q&!Q_N"
    },
    {
      "value": 19.0927167,
      "when": "!RESET_B&D&GATE&!Q&Q_N"
    },
    {
      "value": 21.1249755,
      "when": "!RESET_B&D&!GATE&!Q&Q_N"
    },
    {
      "value": 16.896065,
      "when": "!RESET_B&!D&!GATE&!Q&Q_N"
    },
    {
      "value": 21.697371,
      "when": "RESET_B&D&!GATE&!Q&Q_N"
    },
    {
      "value": 19.1054692,
      "when": "RESET_B&!D&!GATE&Q&!Q_N"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "capacitance": 0.001673,
    "clock": "false",
    "direction": "input",
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    "internal_power": {
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          0.0793701,
          0.223607,
          0.629961,
          1.77477,
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          0.0061011,
          0.0060884,
          0.0062067,
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      },
      "rise_power power_inputs_1": {
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          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
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        "values": [
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          0.0017915,
          0.0021493
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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    "timing": [
      {
        "fall_constraint vio_3_3_1": {
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            2.5,
            5.0
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          "index_2": [
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              -0.2767272,
              0.0093242
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        },
        "related_pin": "GATE",
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          "index_2": [
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          "values": [
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              0.234959,
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              0.9270895
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            [
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              0.6864075,
              0.8937236
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_falling",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_3_3_1": {
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            5.0
          ],
          "index_2": [
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            5.0
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          "values": [
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            [
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              0.3008688,
              0.0148174
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        },
        "related_pin": "GATE",
        "rise_constraint vio_3_3_1": {
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            0.01,
            2.5,
            5.0
          ],
          "index_2": [
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            5.0
          ],
          "values": [
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              -0.4484395,
              -0.9552265,
              -1.1881774
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            [
              -0.1101094,
              -0.6205586,
              -0.8480163
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            [
              0.005654,
              -0.5029642,
              -0.7359151
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_falling",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin GATE": {
    "capacitance": 0.001644,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.001607,
    "internal_power": {
      "fall_power power_inputs_1": {
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          0.01,
          0.0281727,
          0.0793701,
          0.223607,
          0.629961,
          1.77477,
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          0.0132306,
          0.0131833,
          0.013187,
          0.013334,
          0.013885
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      },
      "rise_power power_inputs_1": {
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          0.01,
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          0.0793701,
          0.223607,
          0.629961,
          1.77477,
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        "values": [
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          0.0077772,
          0.0077057,
          0.0076468,
          0.0076229
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00168,
    "timing": {
      "related_output_pin": "Q",
      "related_pin": "GATE",
      "rise_constraint constraint_3_0_1": {
        "index_1": [
          0.01,
          2.5,
          5.0
        ],
        "values": [
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          4.1666666,
          8.3333333
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      },
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
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        "fall_power power_outputs_1": {
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              -0.0013221,
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              -0.0014018,
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              -0.0088583,
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              -0.0017273,
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        },
        "related_pin": "D",
        "rise_power power_outputs_1": {
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      },
      {
        "fall_power power_outputs_1": {
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        },
        "related_pin": "GATE",
        "rise_power power_outputs_1": {
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      },
      {
        "fall_power power_outputs_1": {
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        "related_pin": "RESET_B",
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      }
    ],
    "max_capacitance": 0.1822,
    "max_transition": 1.501096,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
      {
        "cell_fall del_1_7_7": {
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        "cell_rise del_1_7_7": {
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}