| { |
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| "cell_footprint": "and4", |
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| "driver_waveform_rise": "ramp", |
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| }, |
| { |
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| }, |
| { |
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| }, |
| { |
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| { |
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| { |
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| }, |
| { |
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| }, |
| { |
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| }, |
| { |
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| }, |
| { |
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| { |
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| { |
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| { |
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| { |
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| { |
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| ], |
| "pg_pin VGND": { |
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| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
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| "pg_pin VPB": { |
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| "voltage_name": "VPB" |
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| "pg_pin VPWR": { |
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| "pin X": { |
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| }, |
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