{
  "area": 10.0096,
  "cell_footprint": "and3b",
  "cell_leakage_power": 0.003178133,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
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      "value": 0.0036598,
      "when": "!A_N&!B&C"
    },
    {
      "value": 0.0035981,
      "when": "!A_N&!B&!C"
    },
    {
      "value": 0.0001005,
      "when": "!A_N&B&C"
    },
    {
      "value": 0.0036669,
      "when": "!A_N&B&!C"
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    {
      "value": 0.0035837,
      "when": "A_N&!B&C"
    },
    {
      "value": 0.0035826,
      "when": "A_N&!B&!C"
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    {
      "value": 0.0036495,
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    {
      "value": 0.0035841,
      "when": "A_N&B&!C"
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  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001329
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  "pin B": {
    "capacitance": 0.001395,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001372,
    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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    "max_transition": 1.5,
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    "related_power_pin": "VPWR",
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  "pin C": {
    "capacitance": 0.001386,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.00133,
    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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  "pin X": {
    "direction": "output",
    "function": "(!A_N&B&C)",
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      {
        "fall_power power_outputs_1": {
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        "related_pin": "B",
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    "max_capacitance": 0.195933,
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    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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        "cell_rise del_1_7_7": {
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