{
  "area": 10.0096,
  "cell_footprint": "and2b",
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  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
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    "voltage_name": "VGND"
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    "voltage_name": "VNB"
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    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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    "related_power_pin": "VPWR",
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    "internal_power": {
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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}