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"cell_footprint": "and2", | |
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"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
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{ | |
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{ | |
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{ | |
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], | |
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"voltage_name": "VGND" | |
}, | |
"pg_pin VNB": { | |
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"voltage_name": "VNB" | |
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"voltage_name": "VPB" | |
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"voltage_name": "VPWR" | |
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"clock": "false", | |
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"function": "(A&B)", | |
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[ | |
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[ | |
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[ | |
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[ | |
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"power_down_function": "(!VPWR + VGND)", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"timing": [ | |
{ | |
"ccsn_first_stage": { | |
"dc_current ccsn_dc": { | |
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