{
  "area": 11.2608,
  "cell_footprint": "a2bb2o",
  "cell_leakage_power": 0.001766576,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
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      "value": 0.0012067,
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    },
    {
      "value": 0.0012067,
      "when": "!A1_N&!A2_N&!B1&!B2"
    },
    {
      "value": 0.0012054,
      "when": "!A1_N&!A2_N&B1&B2"
    },
    {
      "value": 0.0012067,
      "when": "!A1_N&!A2_N&B1&!B2"
    },
    {
      "value": 0.0026592,
      "when": "!A1_N&A2_N&!B1&B2"
    },
    {
      "value": 0.0026174,
      "when": "!A1_N&A2_N&!B1&!B2"
    },
    {
      "value": 0.0010849,
      "when": "!A1_N&A2_N&B1&B2"
    },
    {
      "value": 0.0026994,
      "when": "!A1_N&A2_N&B1&!B2"
    },
    {
      "value": 0.0017244,
      "when": "A1_N&!A2_N&!B1&B2"
    },
    {
      "value": 0.0016827,
      "when": "A1_N&!A2_N&!B1&!B2"
    },
    {
      "value": 0.0001493,
      "when": "A1_N&!A2_N&B1&B2"
    },
    {
      "value": 0.0017653,
      "when": "A1_N&!A2_N&B1&!B2"
    },
    {
      "value": 0.0026582,
      "when": "A1_N&A2_N&!B1&B2"
    },
    {
      "value": 0.0026165,
      "when": "A1_N&A2_N&!B1&!B2"
    },
    {
      "value": 0.0010833,
      "when": "A1_N&A2_N&B1&B2"
    },
    {
      "value": 0.0026991,
      "when": "A1_N&A2_N&B1&!B2"
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  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
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  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
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    "capacitance": 0.001681,
    "clock": "false",
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      "rise_power power_inputs_1": {
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        "values": [
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001743
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  "pin B2": {
    "capacitance": 0.001759,
    "clock": "false",
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    "fall_capacitance": 0.001702,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
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      "rise_power power_inputs_1": {
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001816
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  "pin X": {
    "direction": "output",
    "function": "(B1&B2) | (!A1_N&!A2_N)",
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        "fall_power power_outputs_1": {
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      {
        "fall_power power_outputs_1": {
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      {
        "fall_power power_outputs_1": {
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        "fall_power power_outputs_1": {
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