{
  "area": 8.7584,
  "cell_footprint": "a21o",
  "cell_leakage_power": 0.001221859,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "leakage_power": [
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      "value": 0.0001406,
      "when": "!A1&!A2&B1"
    },
    {
      "value": 0.0002552,
      "when": "!A1&!A2&!B1"
    },
    {
      "value": 0.0001406,
      "when": "!A1&A2&B1"
    },
    {
      "value": 0.0002652,
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    },
    {
      "value": 0.0001406,
      "when": "A1&!A2&B1"
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    {
      "value": 0.0002628,
      "when": "A1&!A2&!B1"
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    {
      "value": 0.0084265,
      "when": "A1&A2&B1"
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    {
      "value": 0.0001433,
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  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
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    "clock": "false",
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      "rise_power power_inputs_1": {
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    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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  "pin A2": {
    "capacitance": 0.002048,
    "clock": "false",
    "direction": "input",
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    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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  "pin B1": {
    "capacitance": 0.002117,
    "clock": "false",
    "direction": "input",
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    "internal_power": {
      "fall_power power_inputs_1": {
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        "values": [
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      "rise_power power_inputs_1": {
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        "values": [
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          -0.0012744,
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          -0.0012802
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    },
    "max_transition": 5.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002259
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  "pin X": {
    "direction": "output",
    "function": "(A1&A2) | (B1)",
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        "fall_power power_outputs_1": {
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      {
        "fall_power power_outputs_1": {
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    ],
    "max_capacitance": 0.345622,
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    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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        "cell_rise del_1_7_7": {
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        "fall_transition del_1_7_7": {
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