| { |
| "area": 18.768, |
| "cell_footprint": "a21boi", |
| "cell_leakage_power": 6.383434, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
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| { |
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| }, |
| { |
| "value": 4.1534483, |
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| }, |
| { |
| "value": 10.8837828, |
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| }, |
| { |
| "value": 4.1532666, |
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| { |
| "value": 9.9378976, |
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| { |
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| { |
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| }, |
| { |
| "value": 1.0489438, |
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| ], |
| "pg_pin VGND": { |
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| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
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| "voltage_name": "VPB" |
| }, |
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| "voltage_name": "VPWR" |
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| 0.0316228, |
| 0.1, |
| 0.316228, |
| 1.0, |
| 3.16228, |
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| "pin A2": { |
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| }, |
| "max_transition": 10.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| }, |
| "pin B1_N": { |
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| "internal_power": { |
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| 0.0129204, |
| 0.0136107 |
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| }, |
| "rise_power power_inputs_1": { |
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| 0.0316228, |
| 0.1, |
| 0.316228, |
| 1.0, |
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| 0.0078244, |
| 0.0094548 |
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| } |
| }, |
| "max_transition": 10.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002501 |
| }, |
| "pin Y": { |
| "direction": "output", |
| "function": "(!A1&B1_N) | (!A2&B1_N)", |
| "internal_power": [ |
| { |
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| }, |
| "related_pin": "A1", |
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| { |
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| [ |
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| }, |
| "related_pin": "A2", |
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| }, |
| { |
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| [ |
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| [ |
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| }, |
| "related_pin": "B1_N", |
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| } |
| ], |
| "max_capacitance": 0.676737, |
| "max_transition": 9.991367, |
| "power_down_function": "(!VPWR + VGND)", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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