)]}'
{
  "commit": "c70c051bf1e4d7eecb28cf125ebf5465aaf86060",
  "tree": "8ab660cdb41d72eb97b82a514dc453730ec83ae1",
  "parents": [
    "a01b59602054950875ee9b981b778087c02e8ed1",
    "fa8d392b63c607ce42af14683782276623890130"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing include path.\n\nThe include lines previously had,\n`include \"sky130_fd_sc_hd__o221a.pp.functional.v\"`\nbut the actual filename is\n`include \"sky130_fd_sc_hd__o221a.functional.pp.v\"`.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}