| commit | 9b8d061bb2dcdeaf367aacf4b592f6ca05df77df | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | af2280258e58b833ecec11d442f56c7a6622a26f | |
| parent | c70c051bf1e4d7eecb28cf125ebf5465aaf86060 [diff] | |
| parent | 23c9281bdb9d2bbcc75a2efa0b8077ec9f77fca6 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>