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| 2.1 |
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| "comp_attribute output_voltage_range": [ |
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| "driver_waveform_rise": "ramp", |
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| "leakage_power": [ |
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| "voltage_name": "LOWLVPWR" |
| }, |
| "pg_pin VGND": { |
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| "voltage_name": "VGND" |
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| "pg_pin VPB": { |
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| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
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| "std_cell_main_rail": "true", |
| "voltage_name": "VPWR" |
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| "clock": "false", |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "LOWLVPWR", |
| "rise_capacitance": 0.006368 |
| }, |
| "pin X": { |
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| "related_power_pin": "VPWR", |
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| "timing_type": "combinational" |
| } |
| } |
| } |
