tree af2280258e58b833ecec11d442f56c7a6622a26f
parent c70c051bf1e4d7eecb28cf125ebf5465aaf86060
parent 23c9281bdb9d2bbcc75a2efa0b8077ec9f77fca6
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>