{
  "area": 15.0144,
  "cell_footprint": "dlxtp",
  "cell_leakage_power": 0.005345429,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "latch IQ,IQ_N": {
    "data_in": "D",
    "enable": "GATE"
  },
  "leakage_power": [
    {
      "value": 0.0064445,
      "when": "D&GATE&Q"
    },
    {
      "value": 0.0041898,
      "when": "!D&!GATE&!Q"
    },
    {
      "value": 0.0042954,
      "when": "!D&GATE&!Q"
    },
    {
      "value": 0.0064261,
      "when": "D&!GATE&Q"
    },
    {
      "value": 0.0063786,
      "when": "D&!GATE&!Q"
    },
    {
      "value": 0.0043382,
      "when": "!D&!GATE&Q"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "capacitance": 0.001615,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001523,
    "internal_power": {
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        "index_1": [
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
          1.5
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          0.0073951,
          0.0073557,
          0.0072649,
          0.0070557
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      "rise_power power_inputs_1": {
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          0.0230506,
          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0019795,
          0.0015804
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    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001708,
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      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
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            0.5,
            1.5
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          "index_2": [
            0.01,
            0.5,
            1.5
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          "values": [
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              0.2931296,
              0.657306
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              -0.2061217,
              0.0422832,
              0.4040182
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              -0.3463073,
              0.0154277
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        "related_pin": "GATE",
        "rise_constraint vio_3_3_1": {
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          "index_2": [
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              0.5028952
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              0.2913066
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_falling",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
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            0.5,
            1.5
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          "index_2": [
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            1.5
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              -0.030959,
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              0.3625143,
              -0.0016621
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        "related_pin": "GATE",
        "rise_constraint vio_3_3_1": {
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            0.5,
            1.5
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          "index_2": [
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            1.5
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          "values": [
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              -0.3019551,
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              -0.6520853
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            [
              -0.1255716,
              -0.2946309,
              -0.4757018
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            [
              0.110431,
              -0.0464212,
              -0.2372578
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_falling",
        "violation_delay_degrade_pct": 10
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    ]
  },
  "pin GATE": {
    "capacitance": 0.001602,
    "clock": "true",
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    "fall_capacitance": 0.001504,
    "internal_power": {
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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          0.0154247
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      "rise_power power_inputs_1": {
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          0.01,
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0091105,
          0.0084539
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.0017,
    "timing": {
      "related_output_pin": "Q",
      "related_pin": "GATE",
      "rise_constraint constraint_3_0_1": {
        "index_1": [
          0.01,
          0.5,
          1.5
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        "values": [
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      },
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
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  },
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    "direction": "output",
    "function": "IQ",
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        "fall_power power_outputs_1": {
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        "related_pin": "D",
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      {
        "fall_power power_outputs_1": {
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    "max_capacitance": 0.101634,
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    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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        "cell_rise del_1_7_7": {
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        "timing_sense": "positive_unate",
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