{
  "area": 21.2704,
  "cell_footprint": "dlrbn",
  "cell_leakage_power": 0.008013925,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "latch IQ,IQ_N": {
    "clear": "!RESET_B",
    "data_in": "D",
    "enable": "!GATE_N"
  },
  "leakage_power": [
    {
      "value": 0.0100504,
      "when": "RESET_B&D&!GATE_N&Q&!Q_N"
    },
    {
      "value": 0.0064586,
      "when": "RESET_B&!D&GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0065518,
      "when": "!RESET_B&!D&!GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0065637,
      "when": "RESET_B&!D&!GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0100301,
      "when": "RESET_B&D&GATE_N&Q&!Q_N"
    },
    {
      "value": 0.0088121,
      "when": "!RESET_B&D&!GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0064467,
      "when": "!RESET_B&!D&GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0086354,
      "when": "!RESET_B&D&GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0086473,
      "when": "RESET_B&D&GATE_N&!Q&Q_N"
    },
    {
      "value": 0.0079432,
      "when": "RESET_B&!D&GATE_N&Q&!Q_N"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin D": {
    "capacitance": 0.001614,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001522,
    "internal_power": {
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.016444,
          0.0163907,
          0.0162681
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      "rise_power power_inputs_1": {
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.007666,
          0.0077661,
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    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001707,
    "timing": [
      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
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            0.5,
            1.5
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          "index_2": [
            0.01,
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              -0.0185404,
              0.211554,
              0.5708476
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        },
        "related_pin": "GATE_N",
        "rise_constraint vio_3_3_1": {
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          "index_2": [
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          "values": [
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              0.107599,
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              0.4516256
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            [
              -0.1320658,
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              0.2107402
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_3_3_1": {
          "index_1": [
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            0.5,
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          ],
          "index_2": [
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            0.5,
            1.5
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          "values": [
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              -0.1579121,
              -0.4075378,
              -0.7753763
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            [
              -0.0425638,
              -0.2921895,
              -0.660028
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            [
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              -0.1745951,
              -0.5387715
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        },
        "related_pin": "GATE_N",
        "rise_constraint vio_3_3_1": {
          "index_1": [
            0.01,
            0.5,
            1.5
          ],
          "index_2": [
            0.01,
            0.5,
            1.5
          ],
          "values": [
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              -0.2824238,
              -0.4490417,
              -0.6337748
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            [
              -0.0816263,
              -0.2470234,
              -0.4305358
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            [
              0.1617005,
              -0.006138,
              -0.1920918
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin GATE_N": {
    "capacitance": 0.001621,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.001541,
    "internal_power": {
      "fall_power power_inputs_1": {
        "index_1": [
          0.01,
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0160263,
          0.0158629,
          0.015486
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      },
      "rise_power power_inputs_1": {
        "index_1": [
          0.01,
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          0.0531329,
          0.122474,
          0.282311,
          0.650743,
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        "values": [
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          0.0098309,
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          0.0096681,
          0.0094062,
          0.0088029
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      }
    },
    "max_transition": 1.5,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.0017,
    "timing": {
      "fall_constraint constraint_3_0_1": {
        "index_1": [
          0.01,
          0.5,
          1.5
        ],
        "values": [
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          0.8333333,
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      },
      "related_output_pin": "Q",
      "related_pin": "GATE_N",
      "sim_opt": "runlvl=5 accurate=1",
      "timing_type": "min_pulse_width",
      "violation_delay_degrade_pct": 10
    }
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": [
      {
        "fall_power power_outputs_1": {
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          "index_2": [
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              -0.0049613,
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              -0.0198608,
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              -0.004942,
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              -0.0199223,
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              -0.0048792,
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        },
        "related_pin": "D",
        "rise_power power_outputs_1": {
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      },
      {
        "fall_power power_outputs_1": {
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        },
        "related_pin": "GATE_N",
        "rise_power power_outputs_1": {
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      },
      {
        "fall_power power_outputs_1": {
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        "related_pin": "RESET_B",
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      }
    ],
    "max_capacitance": 0.101634,
    "max_transition": 1.517109,
    "power_down_function": "(!VPWR + VGND)",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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        "cell_fall del_1_7_7": {
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        "cell_rise del_1_7_7": {
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}